Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Setup & Hold -> what's the physical explanation?

Status
Not open for further replies.

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
Hi All,

What's the physical explanation for the Setup & Hold requirements?

Thank you!
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
19,772
Helped
4,350
Reputation
8,709
Reaction score
4,314
Trophy points
1,393
Activity points
130,852
Hi,

You are talking about timing?

Setup time.
For example a D-FF. It has a data input and a clock input. Often you first must apply the data, then th clock edge. Data must be set up before clock edge.

Hold time:
Imagine a three state output buffer. There is an enable pin. When you disable the buffer, then for a short time the buffer is still low impedance before becoming high impedance. This is called hold time.

Klaus
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
Imagine a three state output buffer. There is an enable pin. When you disable the buffer, then for a short time the buffer is still low impedance before becoming high impedance. This is called hold time.
Could you explain more please? Don't catch this point...

Actually I was asked in the interview "What's the physical explanation for the Setup and Hold time requirements?" As I understand, they expected to hear about CMOS behavior or internal structure of FlipFlop (or Latch).
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
19,772
Helped
4,350
Reputation
8,709
Reaction score
4,314
Trophy points
1,393
Activity points
130,852
Hi,

I just reviewed my statement about "hold time". I was wrong on that. It has nothing to do with three state buffers.

Hold time:
For example a D-FF. It has a data input and a clock input. Often you need to hold the data after the clock edge for a short time.

***
here a datasheet of a D-FF:

You may find the values for setup tim and hold time in a table on page10. Also you may find a timing diagram Figure8 on page11.

***
Again, sorry for the mistake, that eventually confused you.

Klaus
 

shobhit

Member level 2
Joined
Oct 4, 2007
Messages
49
Helped
13
Reputation
26
Reaction score
10
Trophy points
1,288
Location
India
Activity points
1,643
Hi,

A Flip Flop is made up of master latch and a slave latch.

Setup Time: We need to provide enough time for the input capacitance of Master latch to be charged up or discharged down, before the Master latch captures the data. To ensure that this happens ,we have a setup time requirement. If we violate this setup time requirement. We cannot be sure what value will be captured by the master latch, may be 0, may be 1..

Hold time: Even after the Master latch has captured the data, the clock of Master gets disabled and the clock of slave gets enabled, now we should provide Enough time for the master latch to be fully disabled and slave latch fully enabled. If the data at input of Master latch changes and at that instant the clock of master latch had not gone into inactive level, then we might enter into metastability. To ensure this we have a hold check in a flip flop.
 
  • Like
Reactions: ivlsi

    ivlsi

    Points: 2
    Helpful Answer Positive Rating

dpaul

Advanced Member level 4
Joined
Jan 16, 2008
Messages
1,480
Helped
307
Reputation
614
Reaction score
303
Trophy points
1,373
Location
Germany
Activity points
11,080
Actually I was asked in the interview "What's the physical explanation for the Setup and Hold time requirements?" As I understand, they expected to hear about CMOS behavior or internal structure of FlipFlop (or Latch).

This part of your question makes me more curious.
If I were you, I would have asked the interviewer what is meant by "physical explanation".
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
If the data at input of Master latch changes and at that instant the clock of master latch had not gone into inactive level, then we might enter into metastability.
Why? Can you explain physically why a metastability happens?
 

SunnySkyguy

Advanced Member level 5
Joined
Sep 26, 2007
Messages
6,744
Helped
1,675
Reputation
3,348
Reaction score
1,644
Trophy points
1,413
Location
Richmond Hill, ON, Canada
Activity points
50,737
Why? Can you explain physically why a metastability happens?

It's a race to sample and store data that is changing at the same time (clock edge). The precise relative latency of the device and signals determines if the outcome of the race is guaranteed ( to be late or early) or whether it is uncertain hence called metastable.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top