Could you explain more please? Don't catch this point...Imagine a three state output buffer. There is an enable pin. When you disable the buffer, then for a short time the buffer is still low impedance before becoming high impedance. This is called hold time.
Actually I was asked in the interview "What's the physical explanation for the Setup and Hold time requirements?" As I understand, they expected to hear about CMOS behavior or internal structure of FlipFlop (or Latch).
Why? Can you explain physically why a metastability happens?If the data at input of Master latch changes and at that instant the clock of master latch had not gone into inactive level, then we might enter into metastability.
Why? Can you explain physically why a metastability happens?