how to fix setup violation synthesis
Sandeep,
Depends on what you mean by 'submitting your design'.
If you mean submitting your gate level netlist for backend, then fix all your setup. Backend can take care of hold easily.
If you mean submitting your layout to fab (taping out your design), then fix all your hold, since a silicon with hold violation is as good as a dead chip.
If your chip has only setup violations, you can run your chip slower and find all functional bugs, then push for bug fixes and timing fixes on your next tapeout.
If your chip has a hold time problem, then you have to respin your chip before you can do any debug.