setup violation can be resolved by running system at a lower clock if possible... hold time violation can be reduced by adding buffers between FF's on data path.
hi vivek,
There is no question of choice between the two. Bith can be corrected. The setup violation can be corrected by running your design at lower frequency or yes redesign your logic so that it gives better performance than the original one.
Hold violation is not dependent on the freq. of operation. That can be eliminated by lenghtning the trace in P&R or by adding buffers in the data path so that the data arrives a little late with respect to the active clock edge.
Hi, this discussion has been done earlier and concluded like this:
As, set-up violations can be corrected even after design is implemented/prototyped, by running it at a reduced clock frequency; Hold-time violations need buffers to be added in the critical path (data) & so cannot be rectified after implementation. So, Hold-time violation is an obvious choice. what do the teachers say?
I think selecting set-up violation is better.bcoz as told earlier set-up can be fixed by reducing the operting frequence.if we are unable to fix the hold problem ,we cannot proceed further