Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

setup and hold time for latch

Status
Not open for further replies.

viswanadh_babu

Member level 2
Joined
Apr 1, 2008
Messages
47
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Activity points
1,575
Hi ,

I know what and how a setup & hold times for flipflop are defined and calculated?
But, i wanted know the same foe latch .
Plz help me
Regards,
k.viswanadh babu
 

As u know the latch to level is a level sensitive here below is the latch to latch setup and hold.
Setup: It will be the time required for the data not to change before the capture clock pulse becomes inactive.
Hold: It will be the time required for the data not to change after the capture clock has become inactive.

It would help if u put a diagram and analyse it.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top