I think it is a common mistake to assume that meeting setup time with slow corner can assure the setup time to meet with fast corner.
In the most case, it is true, but not always.
The most commonly seen example is the timing analysis on the interface signals.
Suppose you have both of clock and data comming from outside of the chip. CLock tree is very deep and data path is so so deep. In this scenario, running STA with slow corner will likely give you a greater slack than fast corner, because of the deep clock tree.
here is the example.
Assume the following timing spec.
Clock pin to CK pin of the most critical flop : 5ns(slow corner)
Data pin to D pin of the same flop : 4ns(slow corner)
clock cycle : 2ns
If the clock and data comes into the chip at the same time, they have 3ns slack(ignoring setup time of the flop).
Now let's say fast corner is twice as fast as slow corner. This makes clock path 2.5ns, and data path 2ns.. Well, this makes the setup slack 2.5ns, which is lesser slack than the slow corner. You see the picture.
I have seen this issue on every chips I worked on, though it was opposite case. i.e. hold timing is met with fast corner, but violates big time with slow corner. The opposite to this case, meeting setup with slow and violating it with fast, could happen in theory.