settling of SC integrator

[jiangxb]

hi

i'm designing a SC sigma-delta modulator. when i simulate the SC circuit in transistor-level, i find that there is overshoot in the output of integrator when settling. i have designed the operational amplifier with enough bandwidth(60MHz, and the sampling frequency is 1MHz) and phase margin(>70°).

where the overshoot is from? i appreciate that anyone can give me some hints.

the plot below is the differential voltage of integrator output.

 

[LvW]

Hi jiangxb

as you have simulated the opamp on transistor level - how did you realize the switches ? I suppose, also on transistor level, don´t you ? What about non-ideal effects (parasitics, feedthrough) ? Or have you used ideal switches ?

 

[jiangxb]

Hi jiangxb

as you have simulated the opamp on transistor level - how did you realize the switches ? I suppose, also on transistor level, don´t you ? What about non-ideal effects (parasitics, feedthrough) ? Or have you used ideal switches ?

yes, i construct the switches in transistor-level using the transmission gate. i guess that the on-resistance of switches influences the settling of integrator, but the capacitors all are small. the other non-ideal effects of switch, such as parasitics, feedthrough, nonlinearity, can induce this overshoot?

 

[ricklin]

If the on-resistance and the cap's RC close to your 2nd pole that may be a reason. And actually the overshoot is only about 0.2% and settled withing o.5us, I think if your sampling rate is only 1MHz it's ok even you don't need to care it at all.

 

[LvW]

If the on-resistance and the cap's RC close to your 2nd pole that may be a reason. And actually the overshoot is only about 0.2% and settled withing o.5us, I think if your sampling rate is only 1MHz it's ok even you don't need to care it at all.

Yes, I agree. Some influence from non-ideal properties will be the cause.
However, I suppose the originator speaks about the spike at the END of the clock period. And that´s about 1%.

 

[naalald]

Hi jiangxb,
If you mean the peak at the end of the settling, it might be the cause of the output common-mode voltage maladjustment. Are you sure about the output common-mode voltage whether it is set well enough by the common-mode feedback circuit?

 

[jiangxb]

thanks for your all reply.

in fact for clarity i have extended the sampling time to 10us, so the value at the end of sampling can be though as the final value. when sampling 1us the settling is bad, and the odd harmonic distortion is obvious. i also use ideal opamp with infinite bandwidth for simulation, and the overshoot exist yet.

 

[haoshs]

what is exactly the reason for overshoot?

 

[love_analog]

I have had an issue before. Once you put an opamp in closed loop, you may get an additional pole at the input of the opamp if you resistive feedback and input resistor is large.
In that case, I made my opamp simpler (1 pole instead of 2) and made the input pole the dominant one..