Setting Width for D Flip Flop

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nilay shah

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hi,
I am designing D FF,
but i know rise and fall time so how to decide Width of NMOS and PMOS to achieve that delay.

Is there any method or only we have to do try and error?

please reply urgent.
 

Are you doing it at transistor level? Such infos are provided by foundries in their netlists. You can design it using stdcells also.
 

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