sarfaraz.ahmed
Junior Member level 1
Hi,
can anyone help how to set Constraints of fanin and then save that cone ? actually, I traverse back from my output to input and I want to list all gates comes under that output cone ?
Is there any setting in tcl file then please share here. I below show the tcl file which i write but I think something is missing for making the proper cone.
Thanking in the anticipation
can anyone help how to set Constraints of fanin and then save that cone ? actually, I traverse back from my output to input and I want to list all gates comes under that output cone ?
Is there any setting in tcl file then please share here. I below show the tcl file which i write but I think something is missing for making the proper cone.
Code:
## Define the search path
set_attribute lib_search_path /home/sarfaraz.ahmed/techlib/FreePDK45/osu_soc/lib/source/signalstorm/files/
## This defines the library to use
set_attribute library gscl45nm.lib
## Read in verilog cod
read_hdl /home/sarfaraz.ahmed/RC/top.v
# This command to exclude the cell
set_attribute avoid true FAX1 XOR* OR* XNOR* NOR* HAX1 OAI* AOI* AND* BUF* MUX*
#set_attribute preserve true NAND2X1
## This creates a technology-independent schematic
elaborate
##set_attribute avoid true
## Create a technology-dependent schematic
synthesize -to_mapped
## Write out synthesized verilog netlist
write -mapped > top_synth.v
## Write out the SDC file we will take into the place n route tool
write_sdc > ./encounter/top_synth.sdc
## setting constraints for cone of n_1 output
dc::all_fanin -to n_1