Apr 27, 2018 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Hello, In VHDL, Is it possible to set attributes to VHDL ports? I know the syntax for setting an attribute to a signal - but what about a port?
Hello, In VHDL, Is it possible to set attributes to VHDL ports? I know the syntax for setting an attribute to a signal - but what about a port?
Apr 27, 2018 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 yes. In the same way you assign attribute to signal: attribute keep of some_port : signal is "true";
Apr 29, 2018 #3 V vGoodtimes Advanced Member level 4 Joined Feb 16, 2015 Messages 1,089 Helped 307 Reputation 614 Reaction score 303 Trophy points 83 Activity points 8,730 I've also seen suggestions to use: attribute keep of some_port : port is "true"; Not sure if the tools accept both.
I've also seen suggestions to use: attribute keep of some_port : port is "true"; Not sure if the tools accept both.
Apr 29, 2018 #4 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 attribute keep of some_port : port is "true"; This is exactly what I tried before posting - and it didn't work with Vivado...
attribute keep of some_port : port is "true"; This is exactly what I tried before posting - and it didn't work with Vivado...