in which case can one set_input_delay to output pins? I just met a case: In top level there are two submodules, I just found the scripts set_input_delay to one of submodules' output pin. Can anybody help me to understand this?
if I name register on the left of combo logic as reg_left, and the other as reg_right. Do you mean I should do set_input_delay to reg_left/Q? If this is right, does this mean the input delay set to reg_left is in fact the output delay of reg_left? And is it syntax right in DC to set_input_delay to an output pin? thanks