set_input_delay means ?

Hi guys,
I'm confused about set_input_delay in DC. Does it mean the delay from the signal source through the I/O pad to the input port (no matter the port is register's or gate's) ? Or it means the delay from the signal source through the I/O pad to the first stage's register in the design?

Another question is : if I have two different designed modules A and B, and one output of A is connected to one input of B. What if both output of A and input of B are registered, should the set_input_delay be zero????

sages said:

Hi guys,
I'm confused about set_input_delay in DC. Does it mean the delay from the signal source through the I/O pad to the input port (no matter the port is register's or gate's) ? Or it means the delay from the signal source through the I/O pad to the first stage's register in the design?

Click to expand...

set_input_delay means the delay from signal source (usually clk input of a signal launching flop external to I/O) to the I/O pad

sages said:

Another question is : if I have two different designed modules A and B, and one output of A is connected to one input of B. What if both output of A and input of B are registered, should the set_input_delay be zero????

Click to expand...

The input delay here will be from clk input of a signal launching flop in A to corresponding input port in design B

Think of this way, if input delay is not mentioned, then data path time margin is optimistic as in reality some time will be used up in travelling to input port from source of the signal. Without input delay, your design may be passing setup but in reality if input delay is considered it may violate setup in capturing flop.

Check this thread:
https://www.edaboard.com/threads/235836/

Thank U for ur explanation