set_input_delay in DC

[cnspy]

set_input_delay

In DC, set_input_delay used in seqential design. it set the delay of input ports from clock.

But in the combinational design. which is the reference timing port for the delay calculating?


Thanks in advance.

 

[claint]

set_input_delay example

use set_min_delay and set_max_delay

 

[AlexWan]

set_input_delay -add_delay

This command is applicated on the pins.
Why to plan to use this on your combination design?

Sorry I am confused.

 

[cnspy]

set_input_delay add_delay

First thanks for your reply.

I am the beginner of DC. I just read the man page
of this command and find a example on combinational circuit. So I am not sure how to use
it in combinational circuit.

Thanks in advance.

 

[cnz]

set_input_delay no clock

alternative way is:
Create a virtual clock that has only clock name and no clock source .

 

[cnspy]

set_input_delay set_max_delay

thanks

Now I need to learn the new concept virtual clock.

Any question I will come back to ask from you.

Thanks again.

 

[kenpu]

dc virtual clock

Thanks , But there is a pincple for set_input_delay how many time?
according to the design or according the experience?

 

[shep_dog]

set_input_delay dc_shell

Hi...

Use set_input_delay when the input to your module is delayed (due to logic outside your module and inside another module).

This will let DC know that your logic does not have the entire clock cycle to meet timing.

For example, if the input pin "request" is sent from another module, and that module has decoding logic, arbirtrationl logic, etc .... the input "request" to your module may not get to you until 2 ns later. Therefore, you have the clock_period minus 2 ns to go through your own logic.

Usually, 2 ns of set_input_delay is a good start. But you need to check where the signals are coming from and adjust accordingly.