quake said:hello. Does PT support analog design? or you just view your analog sub_module as
a black-box and just set some input and output constraints for it?
quake said:I am wondering why you use PT to do the job, you are right, and PT is right too.
but the result may not seem that meaningful, why not turn to spice for more accurate delay caculation?
ramakrishna said:Hi
First of all, i don't think PT supports analog design.
coming to the set_input_delay and set_output_delay part if the inputs and outputs in the top level are from the digital submodule, you can assign delay values depending on your time budget. but for ports coming from or going to analog sub module (or macro) you need not set input and output delays. istead, use set_false_path to eliminate them from timing analysis. also u can block the entire analog module from timing analysis. incase if signals are going from analog to digital sub module (as inputs) synchronise them to the digital module's clock and use them. also use set_false_path on these signals and the synchronisers.
i hope this helps.
ramakrishna
carrie said:Since your analog block is treated as a black box, and it's interface timing is represented by ILM model, I think you can use set_input_delay/set_output_delay on top-level ports as usual.
haosg said:Hi, the dc, pt, pc, astro all support set input_delay and output_delay in submodule's ports.
in this time, you dont read behavial model,but read
link library.
for input of the macro, you need set output_delay in top level, for output of the macro, you need set input_delay in top level. all are ok.
haosg said:yes. it is ok.
but better way is create_generated_clock in analog module's clock input port,
thus when do top-level clock tree synthesis, the port will be balanced with other related DFF's.
you can get completely constraitn and better timing .
haosg said:the clock port from analog submodule is a clock source , there is no phase
relationship to the other clocks, so to my way of thinking i can't create generated clock on this port, do you think so?
BTW, about use set_input/output_delay on port of submodule ,
i can't find the related descriptions in sold, even one simple example , can you tell me why you confirm it? Thanks.
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