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set_input_dealy and set_output_dealy for multi clock design constraints

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Full Member level 6
Jul 30, 2010
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Hi all,

I have a design like below,
Let us say, the design contains
CLK1, CLK2 - input clocks
D - data input
Q - data output
SEL - mux selection

if the design contains two sub modules say U1 and U2, for easier under standing I am instantiating the instance like below
DUT U1 (.D(D), .CLK(CLK1), .Q(Q1));
DUT U2 (.D(D), .CLK(CLK2), .Q(Q2));

assign Q = (SEL) ? Q1 : Q2;

Please let me know Which reference clock I can used for set_input_delay constraints for D and SEL input ports?
Also which reference clock I can used for set_output_delay constraints for Q output port?

CLK1 and CLK2 are out of phase and can be same or different freq

I am using the SDC file with set_input_delay delay_value -clock clock_ref [–max] [–min] [–clock_fall] input_list for set input delay and set_output_delay delay_value -clock clock_ref [–max] [–min] [–clock_fall] output_list for set output delay

NOTE : this is not the actual design, actual design is some what complex, that is why I try to explain the scenario by taking simple examples.I am not following the code syntax highlighting, because this is not a complete code. I am using the verilog for coding.
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1. Is it U1 and U2 is the same design/module?
2. Which one of this design is the top module?

Input delay is the delay from another design/module to your design while output delay is the delay from your design to another design/module. Based on your codes, if I consider U1 is the top module, I can generally say that I will put CLK1 for input delay and output delay since it is the the top module.

If you is considering two different module(which means both U1 and U2 are top module for different design), then you must generate the input and output delay separately.
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The input delay for the D and SEL inputs depend on the clock which is used to sample it. If CLK1 is used to sample them, then these constraints have to be given with respect to CLK1, else CLK2. The same logic holds for output delay as well. Find the clock on which that output is driven. Provide the constraint with respect to that clock.

Hi Thank you all for your reply.

@ deepsetan : Here both U1 and U2 are same or different modules (in my real scenario I have used same instances multiple times and different instances too). We cannot say U1 or U2 as top module. Here the U1 and U2 are sub modules which are instantiated under the TOP modules.

@ sharath666 : Here the D input is going to both the U1 and U2 module, so we are sampling the D input with CLK1 in U1 module and with CLK2 in U2 module.
If we are selecting the Q1 then the D input will be driven into the chip using the CLK1 clock and the output Q will be selected as Q1 by using the SEL input.
Similarly if we are selecting the Q2 then the D input will be driven into the chip using the CLK2 clock and the output Q will be selected as Q2 by using the SEL input.

So here the D input can be sampled by CLK1 and CLK2 clock depends up on the SEL input, also the Output can be driven by using the CLK1 or CLK2 depends up on the SEL input.

So whether I need to use the both clock as reference for set input and output delay.

Then you have to go with the worst case delays. It can either be with CLK1 or CLK2.
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