set_case_analysis problem

[vahid_roostaie]

set_case_analysis

Hi!

I haved Muxed two clocks in my design.both of them are coming from input ports.
the selet signal of the mux is generated by a controller that works with CLK1 in an special state and the output of clock MUX is a clock that is used in another seprated controller that drive some other output ports.I can not use set_case_analysis "1 or 0" [get_ports "select signal"] I used get_pins too but the problem remains.

the mux select signal is generated internaly.my questions:

1-do I have to use create_clock to define my input CLK1 and CLK2 ports?

2-do I have to use create_clock to define the MUX output that is a clock itself?

3-do I have to Use create_generated_clock to define the MUX output.if so how?
there is no divide or multiply relation between MUX inputs and output.and the MUx output is just one of the CLK1 and CLK2 based on select signal.would you please write an example form me?

4-If I want to use set_propagate_clock.do I have to use this command for CLK1,CLK2 and MUX output?

5-I want to use set_input_delay and set_output_delay for inputs and outputs how can I use this command?because there are some ports related to each one of these three clocks.

6-if I want to use set_fix_hold for the clocks how can do that?

7-I want to insert clock gating in my design because of power consumption by commands set_clock_gating_style and insert_clock_gating.I have some register banks that works with these three clocks seperately how can I use set_clock_gating_style based on an specified clock or is there any other way to gate all the clock of all registers that have seperated clocks?


I'm waiting to hearing from you ASAP.
thanks

 

[funzero]

mux clock set_case_analysis

i saw a case like this in AMBIT pks 50 document.
two clocks( test_clock adn function_clock ) are added to the circuit by introducing a mux .
they define two clocks and two clock_root.
and set input_delay output_delay related to each clock .

 

[silencer3]

set_case_analysis input -ieee

define clocks at MUX inputs or at their ctsroot

set_case_analysis on mux select line

U need not define clock at mux output

Even if u want to create a generated_clock at mux output, u can do it with a devide by 1 relation. This is perfectly OK, if u want to do.

propagated clock is used on all clocks defined irrespective of their position. all clocks must be propagated.

input & output delays can be set independtly for ports with different clocks. PLS SEARCH FORUMS FOR CONSTRAINTS. i have a post there explaining this.

set_fix_hold can be done for all clocks. DO NOT ATTEMPT THIS, THIS IS BACK_END WORK. Dont do this in front-end.

clock gating is totally a design dependent issue. pls see how u want to do it.