setup violation is usually caused by large data path delay.
data path delay is comprised of combinational logic delay and net delay.
firstly,read you sta report to find out which factor above that makes the main delay on setup violation data path.
secondly,if combinational logic delay is the main delay ,you
can make piplining on this combinational logic block ,also you can make some change in you vhdl or verilog code.
find the process that was synthesize to that combinational logic block ,try to decrease the input bit width ,or try to make the input signal more parallel by use () or use case to replace deep nested if-elses.
thirdly ,if the main factor is net delay,you can do some place and route handly in floorplan tools .
Added after 10 seconds:
setup violation is usually caused by data path delay.
data path delay is comprised of combinational logic and net delay.
firstly,read you sta report to find out which factor above that makes the main delay on setup violation data path.
secondly,if combinational logic is the main delay ,you
can make piplining on this block of combinational logic ,also you can change you vhdl or verilog code.
find the process that was synthesize to that combinational logic,try to decrease the input bit width ,or try to make the input signal more parallel by use () or use case to replace deep nested if elses.
thirdly ,if the main factor is net delay,you can do some place and route handly in floorplan tools .