Set-up & Hold time Violation

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kumar_eee

timing violation width

How to avoid the Set-up & Hold Time violations?....

Full Member level 4
astro hold time

For Setup:

1. pipeline the design.

2. OverCostraint when you synthesize.

3. Increase the synthesize effort.

For Hold:

1. Insert buffer.

2. Increase the synthesize effort.

navaratna

navaratna

Points: 2

hiben

Newbie level 3
timing path violation

datapath stage/clock tree syntesis all affect timing path. it is a big question

cheelgo

Member level 5
design avoid hold time violation

in Gate Simulationk, sometimes will pop up $hold timing violation, I don't exactly know how these kind of width will cause real timing problem or not? Thanks cheelgo Nandy Advanced Member level 4$period timing violation

During logic bringing up period (reset period), a lot of hold/setup errers appear. They are false alarms. Check timing errors after reset.
Disable timing check between synchronizers.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

calm

Full Member level 4
do detail timing constrains in the process of synthesis.
hold vailation can not be avoid completely in the front end design. handle it in layout design.

GoodMan

Full Member level 2
Nandy said:
During logic bringing up period (reset period), a lot of hold/setup errers appear. They are false alarms. Check timing errors after reset.
Disable timing check between synchronizers.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

Hi ,

It need the Key Code !
limited function?

Nandy

Some designs have reverse edge flipflops or latches between two stages to avoid hold time. It can save a lot of buffers inserted by layout tool.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

anan_tv

Junior Member level 1
haiii ,

I have some ideas on this.

the Setup time margin is:

( Tclk - (Tclk-q + T combn + T clkskew) - T su >= 0

the Hold time margin is:

Tclk-q + T combn - T clkskew - T hold >= 0

If both the margins are not satisfied (ie. it becomes -ve), then the setup time and hold time violations occurs.

Due to Setup time violation ==> Previous cycle data will be sampled

Due to Hold time violation ==> Next cycle data will be sampled

To avoid these:

Set up time violation --->

Reduce the operating frequency of the design or pipeline it.

Hold time violation ----->

Introduce delay buffers in the output path.

Take care, byeeeeeee

cheelgo

Hello Nandy, could you help me to explain which kind of timing violation is $with, I have no idea. thank all of you. cheelgo dpk_tottempudi Newbie level 3 To fix the setup and hold violations the aproach is based on the methodology you are fallowing. If you are doing custom design, we cann't completely depend on synthesis tool .. depending upon the code , for ex if it is complex case statements better to handle manually . manual design takes less number of stages than that we usually get from synthesis tool. we can use espresso tool as well to obtain pla form befor doing manual designs.... still lot of options are there depends upon in which case we have negitive slacks. we can use placement changes to fix setup violations. use complex gates aoai,oaoi,aoi,oai etc... signal transitions for the signals which are in critical paths should be as min as possible. Don't blindly increase the cell size to meet timing because self loading comes into the picture. use optimal electrical fanout ( wireload+gate load ) of 4.5 hold issuses.. use delay cells , make use of clock skews , use min sized gates in hold paths.. i will try to answer more if you tell exactly in what env u want to fix paths Nandy Advanced Member level 4 GoodMan said: Nandy said: During logic bringing up period (reset period), a lot of hold/setup errers appear. They are false alarms. Check timing errors after reset. Disable timing check between synchronizers. Nandy www.nandigits.com Netlist Debug/ECO in GUI mode. Hi , It need the Key Code ! limited function? It needs key code to register as commerical usage. If you use it for private, no key code is needed. All features are still funcational. Only that "Not Registered" appears on windows title. Nandy www.nandigits.com Netlist Debug/ECO in GUI mode. Added after 4 minutes: cheelgo said: Hello Nandy, could you help me to explain which kind of timing violation is$with, I have no idea. thank all of you.

cheelgo

Hi Cheelgo

If clock or reset has glitch, it will case \$width violation. Normally it happens when you switch clocks without correct measures.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

hawkbw

Newbie level 2
We will now overview the timing requirements for edge-triggered sequential
circuits, which consist of combinational blocks that lie between D flip-flops.
The basic parameters associated with a flip-flop can be summarized as follows:
The data input of the register, commonly referred to as the D input, must
receive incoming data at a time that is at least units before the onset
of the latching edge of the clock. The data will then be available at the
output node, Q, after the latching edge. The quantity, is referred to
as the setup time of the flip-flop.
The input, D, must be kept stable for a time of units, where is
called the hold time, so that the data is allowed to be stored correctly in the
flip-flop.
Each latch has a delay between the time the data and clock are both available
at the input, and the time when it is latched; this is referred to as the clockto-
Q delay,
In the edge-triggered scenario, let us consider two FF’s, and connected
only by purely combinational paths. Over all such paths let the largest
delay from FF to FF be and the smallest delay be Therefore,
for any path with delay it must be true that
136 TIMING
We will denote the setup time, hold time, and the maximum and minimum
clock-to-Q delay of any arbitrary FF as and and respectively.
For a negative edge-triggered register, the setup and hold time requirements
are illustrated in Figure 7.3. The clock is a periodic waveform that repeats
after every P units of time, called the clock period or the cycle time.
The data is available at the launching FF, after the clock-to-q delay, and
will arrive at the latching FF, at a time no later than For correct
clocking, the data is required arrive one setup time before the latching edge of
the clock at FF as shown in Figure 7.3, i.e, at a time no later than
This leads to the following constraint:
For obvious reasons, this constraint is often referred to as the setup time constraint.
Since this requirement places an upper bound on the delay of a
combinational path, it is also called the long path constraint. A third name
attributable to this is the zero clocking constraint, because the data will not
arrive in time to be latched at the next clock period if the combinational delay
does not satisfy this constraint.
The data must be stable for an interval that is at least as long as the hold
time after the clock edge, if it is to be correctly captured by the FF. Hence,
it is essential to ensure that the new data does not arrive at FF before time
Since the earliest time that the incoming data can arrive is
this gives us the following hold time constraint:
Since this constraint puts a lower bound on the combinational delay on a path,
it is referred to as a short path constraint. If this constraint is violated, then
the data in the current clock cycle is corrupted by the data from the next.
clock cycle; as a result, data is latched twice instead of once in a clock cycle,
and hence it is also called the double clocking constraint. Notice that if the
minimum clock-to-Q delay of FF is greater than the hold time of FF i.e.,
(this condition is not always true in practice), then the right hand
side of the constraint is negative. In this case, since the short path
constraint is always satisfied.

yuenkit

for setup check, overconstraint ur design a bit
e.g. the spec for clock is 10ns, u set it as 8ns.

for hold check, ask ur back end ppl to do rough p&r, and get back the design with timing for u.

synthesis tool doesn't know how your design is routed. what it can do is jst do a timing estimation.

so, it cannt really fix the hold time violation but jst using the estimate value. the best way is to let the place & route guy to do the initial routing, n pass back to u, so u will have a more accurate timing info.

calm

Full Member level 4
for Set-up violations, use dc and pt to solve it.
for Hold Time violations, use astro or appollo

foster_cn

Member level 4
solve set-up violation first with pt, then eliminate hold violation at layout process with astro ro appollo.

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