Set/reset a register in 2 different always@ blocks?(Verilog)

[Sobakava]

simple verilog question

I implemented a pattern generator using Verilog and XC9500 CPLD.

Pattern generated with a clock input.

There is a counter, it counts and there is a Case//endcase block which process counter value and generates pulses...
When counter reaches to 21048, I set it to 0 and next frame starts...

While running my pattern generator freely, there is no problem...

But now I need to control generator with an external trigger...
If a negative or positive edge detected from START pin, it
generator should run for ONCE... Only one turn should be done,
then when it reaches to 21048, it should stop until next START trigger...

input main_clock;
reg counter[14:0];
reg can_read=0;

always @(posedge main_clock)
begin

if (counter==21048)
begin
counter=0;
can_read=0;
end

if (can_read)
begin // begin can read it
counter=counter+1;

case (counter)
1: begin ... end
2: begin ... end
endcase
end
end


I added a reg called as CAN_READ to the design...

input readit;
always @(posedge readit)
begin
can_read=1;
end


As I mentioned, when a positive edge detected at pin READIT, can_read bit will set and main_clk will generate pattern until can_read remains set. When counter reaches to 21048, can_read will be resetted and pattern generator will stop...

Xilinx ISE can implement this design and I load it to chip, but it seems it does not work... Generator always runs and I can not stop it using READIT pin....

Isn't it possible to set/reset a register (can_read) in two different always@(posedge....) blocks?

Any opinion?

 

[karlheinz]

Re: simple verilog question

Is it neccesarry, that your counter counts up, or is it possible
to let him count down ?

 

[Sobakava]

why?

sure I can make it reverse but I'll need to change case--endcase case table...
why?


I am getting this error:
ERROR:NgdBuild:755 - Line 15 in 'counter.ucf': Could not find net(s)
'readit' in the design. To suppress this error specify the correct net
name or remove the constraint. The 'Ignore I\O constraints on Invalid Object
Names' property can also be set ( -aul switch for command line users).
ERRORarsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "counter.ucf".


always @(posedge readit)
begin
can_read=1;
end

But if I add a dummy output pin and toggle it in @posedge READIT it does not give this error:

always @(posedge readit)
begin
can_read=1;
dummy=~dummy;
end


WHY?

I suppose ISE removes always @(posedge readit) .... block
when I leave only can_read=1; statement...
can_read reg is used in always @(posedge main_clock) block too.
Is it prohibited? How to solve this?

 

[yeewang]

it is not prohibited. think it over, when u using
always @(posedge readit)
can_read = 1;
there's only one possible value for can_read, it obviously should be optimized to a constant one and it's what ISE did to ur code.
You seem new to HDL modeling, u'd better read more books/examples.

 

[llrry]

Re: simple verilog question

after synthesis, check the warning and look up the RTL schematic to find out why the synthesizer remove your design.

 

[Sobakava]

Re: simple verilog question

I'll try to what am I trying to do with reducing problem:

Inputs to my chip:
Clock
Read

Outputs :
Frame

I call every count/reset cycle as frame...


A counter runs with the clock, when clock reaches to top, it resets and a single pulse frame signal appears at the output.


I need to do some other tasks during counter is counting.

When a positive edge READ pulse detected (a risign edge and any length pulse) , a ACTIVE bit must be set in next frame, if this bit is set, I do my tasks in @(posedge clock) block....

At the start of next frame, if there is no new READ pulse, this ACTIVE bit must be cleared...

My problem is I can not implement READ / ACTIVE mechanism ... I am not expert in Verilog, I am self learner ;-)


.1.always @(posedge READ)
.2.begin
.3. activate_it=1
.4.end
.5.
.6.always @(posedge CLOCK)
.7.begin
.8. count=count+1
.9. if (count==0)
10. begin
11. if (activate_it)
12. begin
13. activate_it=0;
14. ACTIVE=1
15. end
16. else
17. ACTIVE=0
18. end
19.end


xilinx ise does not accept line 3...

always @(posedge READ)
begin
activate_it=~activate_it;
end
If I do that, I can implement design without errors, but:


always @(posedge READ)
begin
activate_it=1;
end
if I do that, "WARNING:Xst:647 - Input <READ> is never used.
message appears...
ERROR:NgdBuild:755 - Line 16 in 'counter.ucf': Could not find net(s) 'READ' in
ERRORarsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "counter.ucf".


I supposed it is because of optimization, synthesis tool removes it...


I think it is a basic and simple question but I really need help guys...

Attachment image is timing diagram of what I am trying to do...

 

[Quater]

Re: simple verilog question

When counter is reachs to your prefered state you can give hiv him a various number. And an external triger must resets your counter to 0. and thise is start point to new frame out.

 

[Sobakava]

I can't reset counter with external trigger. It should count up to desired fixed value evert time...

 

[Sobakava]

WARNING:Xst:528 - Multi-source in Unit <counter> on signal <activate_it> not replaced by logic
Signal is stuck at GND
ERROR:Xst:415 - Synthesis failed


what does it mean?

 

[nicolepsn]

Re: simple verilog question

:roll:
I think waht yeewang say is right!waht's more,you can't assign value to the same signal in two always.did you do pre-simulation?is it right?

 

[Sobakava]

simple verilog question...helpppp

I understand that,
but I can' set a bit in one "always" and reset it in other always...

synthesis tool can't synthesise this, but,

"WHAT CAN I DO?"

please see the picture, you'll understand what I need...