Serial to parallel converter-problem in Verilog!

[DoraSzasz]

verilog serial to parallel

I want to make a serial to parallel converter for 11 bits with 7495 registers. I made the code for register and for counter,and this is the principal program that cause me problems....I have some errors at parameters declaration and maybe when I put the stimulus,at testing program....I sent you the main program,the counter and the shift register...(the counter and the shift register are correct-I check it)

Thank you a lot for helping me!

Here is the main program:

module Main(
input CLK,
input [10:0] PIN,
output OUT

);

wire Qa,Qb,Qc,Qd,q1,q2,q3,q4,w1,w2,w3,w4;
wire M,L;
reg a;
//first instance
counter inst1(.CLRM(1'b1),.LOADM(L), .ENT(1'b1), .ENP(1'b1), .CLK(clk),.A(1'b0), .B(1'b0), .C(1'b0), .D(1'b0), .Qa(q1), .Qb(q2), .Qc(q3), .Qd(q4), .RCO(a));
always @(q1,q2,q3,q4)
begin
if (Qa==1 & Qb==1 & Qc==1 & Qd==1) assign a=1'b1;
else assign a=1'b0;

end
//second instance for frequency divider
counter inst2(.CLRM(1'b1),.A(1'b0), .B(1'b0), .C(1'b0), .D(1'b0), .ENT(a), .ENP(a), .LOADM(L), .CLK(clk),
.Qa(w1), .Qb(w2), .Qc(w3), .Qd(w4),.RCO(1'b0));
assign M=!(q1|q2|q3|q4);
assign L=!(w3&w2&q4);

reg [10:0] BOUT;

//reg mode;
//
//
//always @(Q1,Q2)
//begin
//if( Q1==4'b0 & Q2==4'b0) assign mode=1'b1;
//end

shiftregister inst3(.mode(M), .clk1(clk), .clk2(clk), .ser(1'b0), .a(PIN[10]), .b(PIN[9]), .c(PIN[8]), .d(PIN[7]), .qA(BOUT[0]), .qB(BOUT[1]), .qC(BOUT[2]), .qD(BOUT[3]));
shiftregister inst4(.mode(M), .clk1(clk), .clk2(clk), .ser(BOUT[3]), .a(PIN[6]), .b(PIN[5]), .c(PIN[4]), .d(PIN[3]), .qA(BOUT[4]), .qB(BOUT[5]), .qC(BOUT[6]), .qD(BOUT[7]));
shiftregister inst5(.mode(M), .clk1(clk), .clk2(clk), .ser(BOUT[7]), .a(PIN[2]), .b(PIN[1]), .c(PIN[0]), .d(1'b0), .qA(BOUT[8]), .qB(BOUT[9]), .qC(BOUT[10]),.qD(OUT));




endmodule


Here is the counter:

module counter(
input CLRM,
input LOADM,
input ENT,
input ENP,
input CLK,
input A,
input B,
input C,
input D,
output Qa,
output Qb,
output Qc,
output Qd,
output RCO
);

reg [3:0] count;
always @(posedge CLK)
if(!CLRM) count<=4'b0;
else if(!LOADM) count <={A,B,C,D};
else count <=count + (ENP&ENT);
assign Qa=count[3];
assign Qb=count[2];
assign Qc=count[1];
assign Qd=count[0];
assign RCO=(ENT)?(count==4'd15):0;

endmodule


Here is the shift register:

module shiftregister(
input mode,
input clk1,
input clk2,
input ser,
input a,
input b,
input c,
input d,
output reg qA,
output reg qB,
output reg qC,
output reg qD
);
wire internalclk=(mode)? clk2:clk1;
always @(negedge internalclk)
begin
qA<=(mode)? a:ser;
qB<=(mode)? b:qA;
qC<=(mode)? c:qB;
qD<=(mode)? d:qC;
end
endmodule