Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity clock is port ( SPI2_CLK : in STD_LOGIC; SPI2_MISO : out STD_LOGIC; SPI2_MOSI : in STD_LOGIC; SPI2_CS : in STD_LOGIC; ); end clock; architecture arch of clock is type sio_size is array(integer range 0 to 63) of STD_LOGIC_VECTOR(15 downto 0); signal sio_in : sio_size; signal sio_out : sio_size; signal count_spi2_bit : integer range 0 to 15 := 0; signal count_spi2_word : integer range 0 to 63 := 0; begin spi2_data: process(SPI2_CLK,SPI2_CS) begin if SPI2_CS = '1' then count_spi2_bit <= 0; count_spi2_word <= 0; elsif rising_edge(SPI2_CLK) then sio_in(count_spi2_word) <= sio_in(count_spi2_word)(14 downto 0) & '0'; sio_out(count_spi2_word) <= sio_out(count_spi2_word)(14 downto 0) & SPI2_MOSI; if count_spi2_bit = 15 then count_spi2_word <= count_spi2_word + 1; end if; count_spi2_bit <= count_spi2_bit + 1; end if; end process; SPI2_MISO <= sio_in(count_spi2_word)(15); end arch;
Reading the vivado synthesis guide I almost get the impression that shared variables are preferred in all cases... Not entirely accurate, but they do have examples that use shared variables that don't seem to need to use them.
Have you ever used Verilog? So much worse.(look at how many examples use non-standard VHDL libraries in Xilinx examples)
Interesting, by "will work" do you mean "will synthesize" or just simulate. Inferring RAMs has historically been quirky.
Code VHDL - [expand] 1 2 3 4 5 elsif rising_edge(SPI2_CLK) then sio_in(count_spi2_word) <= sio_in(count_spi2_word)(14 downto 0) & '0'; sio_out(count_spi2_word) <= sio_out(count_spi2_word)(14 downto 0) & SPI2_MOSI;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity clock is port ( SPI2_CLK : in STD_LOGIC; SPI2_MISO : out STD_LOGIC; SPI2_MOSI : in STD_LOGIC; SPI2_CS : in STD_LOGIC; ); end clock; architecture arch of clock is type sio_size is array(integer range 0 to 63) of STD_LOGIC_VECTOR(15 downto 0); signal sio_in : sio_size; signal sio_out : sio_size; signal count_spi2_bit : integer range 0 to 15 := 0; signal count_spi2_word : integer range 0 to 63 := 0; begin spi2_data: process(SPI2_CLK,SPI2_CS) begin if SPI2_CS = '1' then count_spi2_bit <= 0; count_spi2_word <= 0; sio_out(50) <= sio_out(50) + 1; elsif rising_edge(SPI2_CLK) then sio_in(count_spi2_word) <= sio_in(count_spi2_word)(14 downto 0) & '0'; sio_out(count_spi2_word) <= sio_out(count_spi2_word)(14 downto 0) & SPI2_MOSI; if count_spi2_bit = 15 then count_spi2_word <= count_spi2_word + 1; end if; count_spi2_bit <= count_spi2_bit + 1; end if; end process; SPI2_MISO <= sio_in(count_spi2_word)(15); end arch;
I think your problems have more to do with trying to infer width converting s2p and p2s ram.After reading the other posts again it makes me wonder if some of the results that I have seen are attributed to tool set configuration of block ram. I think that I need to review how the synthesis tool handles inferring block ram.
As a general thought my idea was the following.
configure an array of ram
transmit/receive data from network A and use the array of ram as the buffer
transmit/receive data from network B and use the array of ram as the buffer
Perhaps my thoughts of treating this array of ram as an inferred dual port buffer will not work. I will post a complete test and see what you all think.
I'm pretty sure that using both of these together results in overloaded definitions and will generate warnings or errors.
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
someone with more knowledge of VHDL can probably tell you the exact issues.
I don't think I've ever managed to synthesize an inferred block ram that has width conversion. I haven't tried recently, but all my inferred block rams use the same data width on both ports. Any serial data doesn't go directly to the ram but is instead shifted externally in FFs and is then written into the ram as parallel data.
Is this not a distributed RAM?
type sio_size is array(integer range 0 to 63) of STD_LOGIC_VECTOR(15 downto 0);
signal sio_in : sio_size;
signal sio_out : sio_size;
I will review the ram templates.
I'm pretty sure that using both of these together results in overloaded definitions and will generate warnings or errors.
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
someone with more knowledge of VHDL can probably tell you the exact issues..
std_logic_arith was a de-facto standard, because Synopsys put their package in the IEEE library where it didn't belong (forgot where it's stated, but only ratified packages are allowed in the IEEE library!). In the 90s, Synopsys was a large and arrogant company, so they put their package where they pleased. Ergo, everyone believes it is a IEEE supported package, since it has been in there for nearly 30 years.We use it because it is a supported package, as opposed to std_logic_arith.
A little off-topic, but we don't use numeric_std because of "peer pressure". We use it because it is a supported package, as opposed to std_logic_arith.
std_logic_arith was a de-facto standard, because Synopsys put their package in the IEEE library where it didn't belong (forgot where it's stated, but only ratified packages are allowed in the IEEE library!).
A little off-topic, but we don't use numeric_std because of "peer pressure". We use it because it is a supported package, as opposed to std_logic_arith.
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