Morell
Member level 1
Hi,
-I wrote some codes for these modules(Serial receiver & transmitter).
-Both were synthesized and implemented on Spartan-3 and they worked correctly.
-I want to use them as components in another module so i need the codes to be more modular than now.
This is the Receiver :
and this is the transmitter :
Thanks alot
-I wrote some codes for these modules(Serial receiver & transmitter).
-Both were synthesized and implemented on Spartan-3 and they worked correctly.
-I want to use them as components in another module so i need the codes to be more modular than now.
This is the Receiver :
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 entity Receiver is Port ( Clk : in std_logic; RxD : in std_logic; Parallel_out : out std_logic_vector(7 downto 0)); end Receiver; architecture Behavioral of Receiver is Signal CTR : Std_logic_vector (15 downto 0) := X"0AAA"; Type State is (idle,Receive); Signal CS : state := idle; Signal Data : Std_logic_vector (8 downto 0); begin Parallel_out <= Data(8 downto 1); Process (Clk) Variable i : integer Range 10 downto 0 := 0; Begin if(Clk'event and Clk = '1') then Case CS is When idle => if (RxD = '0') then CS <= Receive; else null; end if; When Receive => CTR <= CTR + X"0001"; if (CTR = X"1555") then if (i < 9) then Data (i) <= RxD; i := i +1; CTR <= X"0000"; else CS <= Idle; CTR <= X"0AAA"; i := 0; end if; end if; end case; end if; end process; end Behavioral;
and this is the transmitter :
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 entity Transmitter is Port ( CLK : in std_logic; ENTER : in std_logic; TXD : out std_logic; DATA : in std_logic_vector(7 downto 0); LED : out std_logic_vector(7 downto 0)); end Transmitter; architecture Behavioral of Transmitter is signal CTR : std_logic_vector (15 downto 0) := X"0000"; Signal Sot : std_logic := '0'; -- Start of Transmission Signal En1 : std_logic := '0'; -- Flag Signal En2 : std_logic := '0'; -- Flag type state is (idle , transmission); signal send : std_logic_vector (9 downto 0); begin LED <= DATA; Send <= '1' & DATA & '0'; process (CLK) variable i :integer range 10 downto 0 := 0 ; begin if (CLK'event and CLK='1') then CTR <= CTR + "0001"; En1 <= Enter; En2 <= En1; if (EN1 = '1' AND EN2 = '1') then Sot <= '1'; end if; if (Sot = '1') then if (CTR = X"1458") then if (i < 10) then TxD <= Send (i); i := i + 1; CTR <= X"0000"; else i := 0; CTR <= X"0000"; SOT <= '0'; end if; end if; end if; end if; end process; end Behavioral;
Thanks alot