1) The max. freq. would be 1/1.8ns = 555.55MHz
5) To make the circuit work at 2.5 GHz (0.4 ns)
5.1) Delay the clocks for output flops, so that skew will be more.
-- for first output flop add 3 more buffers (0.6 ns)
-- for 2nd output flop add 5 more buffers ( 1 ns)
-- for 3rd output flop add 7 more buffers (1.4 ns)
5.2) Delaying the clocks will violate hold requirement. So delay the data paths by adding buffers after the outputs of first stage flops
-- Add 3 buffers (0.6 ns) after the output of 3rd flop of first stage (for which input is c)
-- Add 5 buffers (1 ns) after the output of 4th flop of first stage (for which input is d)
Regards,
Ashish