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The construct is not following the required syntax for aysnchronous + synchronous register action which have been previously suggested in this thread by treger. The order of statements matters.It says "statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition". Actually i can't figure out what is going wrong.
Could please explain some more on it?
The condition for synchronous actions has to be the last condition of the if structure because asynchronous control signals are usually treated with higher priority by the underlying hardware cells
Yes, you can read more about it in text books dedicated to VHDL for hardware synthesis. You can also refer to IEEE Std 1076.3, which tries to define a portable subset of synthesizable VHDL.I think it may be noted as a general rule...