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Selector in Verilog to choose a flavor of design

chainastole

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I have two blocks in design, which functionality is almost similar (about 5% difference) and working together. It is quite obvious it need to be a single RTL file with selectors, activating each instance in the appropriate mode - "this is block A", "this is block B". What should be preferred - defines (`ifdef IS_BLOCK_A) or parameters (if(instance==BLOCK_A))? All relevant considerations are welcome.
 

maxbjurling

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Use parameters. If you want to have two instances with different flavours in a single top level you will have problems using defines.
 

chainastole

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Use parameters. If you want to have two instances with different flavours in a single top level you will have problems using defines.
We are engineers. We argument. What type of problems do you expect?
 

maxbjurling

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We are engineers. We argument. What type of problems do you expect?
Defines are evaluated during compilation. When the RTL file containing the module is compiled (read) the define IS_BLOCK_A will have a value which will determine the result of the `ifdef IS_BLOCK_A statement. Since a module is only compiled once it is not possible to have two instances of a module that sees different define values.

Parameters values, on the other hand, are calculated during elaboration. Then the parameter value for every instance of the module is calculated, and it is possible to have multiple instances of the same module with different parameter values.
 

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