[SOLVED] select and access blocks of ROM in verilog/vhdl

[Dasco]

Hi all,
I wanna be able to write certain data in certain segment ( from a start address to a certain end address) of ROM and with control signals make them accessible.
How can I do that?
thanks in advance

 

[ReComm]

module rominfr (clk, en, addr, data);
input clk;
input en;
input [4:0] addr;
output reg [3:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
4’b0000: data <= 4’b0010;
4’b0001: data <= 4’b0010;
4’b0010: data <= 4’b1110;
4’b0011: data <= 4’b0010;
4’b0100: data <= 4’b0100;
4’b0101: data <= 4’b1010;
4’b0110: data <= 4’b1100;
4’b0111: data <= 4’b0000;
4’b1000: data <= 4’b1010;
4’b1001: data <= 4’b0010;
4’b1010: data <= 4’b1110;
4’b1011: data <= 4’b0010;
4’b1100: data <= 4’b0100;
4’b1101: data <= 4’b1010;
4’b1110: data <= 4’b1100;
4’b1111: data <= 4’b0000;
default: data <= 4’bXXXX;
endcase
end
endmodule

http://asic.co.in/Index_files/verilogexamples.htm#link60

Hope that help you.

 

[Dasco]

thanks for the reply ,
what i want to do is reading the data from ROM and the ROM is 128K so i need another way to do this
( let's say with two variables size and start address of the segment)
and I want to be able to access and mask the partitions with different conditions.
how can i do that?

 

[jhunjhun]

i want to read from ROM in another module.Can anybody help me how to do that?
and Can i store that ROM contents in array??