vijay_nag
Advanced Member level 4
segmentation fault veriloga
Hi!
I am trying to measure the INL of an ADC using the adc_inl_8bit from the ahdlLib. I have customised the verlioga code for the INL measure since my ADC is of 5 bit. When i am simulating in spectre i am getting an error where it states ("Internal error found in spectre during IC analysis, during transient analysis `tran'. Please run `getSpectreFiles' or send the netlist, the spectre log file, the behavioral model files, and any other information that can help identify the problem to support(at) cadence.com. "/h/vijaynag/vij_ahdl/adc_inl_8bit/veriloga/veriloga.va" 178: Segmentation fault.")
I would also like to add that i have successfully simulated the DNL of my ADC using the same method as described above without any errors.
Regards,
Vijay
Hi!
I am trying to measure the INL of an ADC using the adc_inl_8bit from the ahdlLib. I have customised the verlioga code for the INL measure since my ADC is of 5 bit. When i am simulating in spectre i am getting an error where it states ("Internal error found in spectre during IC analysis, during transient analysis `tran'. Please run `getSpectreFiles' or send the netlist, the spectre log file, the behavioral model files, and any other information that can help identify the problem to support(at) cadence.com. "/h/vijaynag/vij_ahdl/adc_inl_8bit/veriloga/veriloga.va" 178: Segmentation fault.")
I would also like to add that i have successfully simulated the DNL of my ADC using the same method as described above without any errors.
Regards,
Vijay