Seeking Help & Exchange: Junior Analog IC Designer Sharing LDO/Bandgap Design, Seeking Guidance & Interview Experience from Seniors

[spacejedigundam]

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Greetings to all the masters and seniors on the forum!​

I am fortunate to have recently received an interview opportunity at my dream company,, and I am actively preparing. Past interview experiences have taught me that the depth and breadth of technical questions significantly impact performance. At times, questions from the interviewer may go beyond my current knowledge or expectations, highlighting blind spots in my understanding of the design and affecting my interview performance.

To prepare more comprehensively, I've thought of a method: sharing my LDO and Bandgap circuit designs and earnestly requesting that seniors here provide questions and feedback on my design. I hope that through discussions with you, I can anticipate the design details and potential issues that interviewers might focus on, thereby filling my knowledge gaps and improving my design skills and interview confidence. This is also an excellent opportunity for mutual learning and collective progress.

Here, I sincerely thank everyone who is willing to spare their valuable time to participate in this discussion. Below are the details of my design. I look forward to your valuable opinions and questions:​

My Design Spec :​

Parameter	3V	5.5V
Output Voltage (V)	1.24V	1.24
PSRR(dB) @100Hz	-89.9	-46.6
Power Dissipation (uA)	86.7	106.4
TC	52.2	40.7
Temperature	-40 ~ 125	-40 ~ 125
Loading (pF)	1pF	1pF

Circuit Architecture Overview:​

My Bandgap circuit primarily consists of the following modules:

• 3 Resistors
• 2 BJTs
• 1 Folded-Cascode Operational Amplifier (OPA)
• 1 P-MOSFET
• 1 Start-Up Circuit Block

(Including a simple circuit diagram would be beneficial for understanding)

Brief Description of Circuit Principle:​

This Bandgap design is based on the principle of temperature coefficient compensation using VBE and VT. The Q2 BJT is used to generate a voltage with a negative temperature coefficient (CTAT). The VBE1 generated by Q1 is processed through the Folded-Cascode OPA, and subtracting VBE2 generates a voltage trend with a positive temperature coefficient (PTAT). By summing the CTAT and PTAT voltages, a reference voltage output with theoretically zero temperature coefficient can be achieved.

Design Concepts and Considerations:​

• BJT Ratio Selection: I chose a BJT ratio of 1:8, mainly to facilitate a 3x3 Common Centroid layout for optimizing the matching characteristics of the BJTs. According to theoretical formulas, the corresponding ratio of R2 to R3 resistors is 9.
• Operational Amplifier Selection: The Folded-Cascode OPA was chosen for its high gain, which helps ensure the stability of the Virtual Short, and also provides a better phase margin. However, its input swing is limited by the Cascode structure, which is a trade-off in the design.
• Start-up Circuit: A start-up circuit is essential in this design to ensure that the circuit powers on correctly. In some cases, node voltages in the circuit might cause transistors to turn off, preventing any current flow and thus failing to establish a stable bias point. The role of the start-up circuit is to provide initial current to ensure the Bandgap circuit can operate normally.
• Resistor Material: Poly resistors were chosen for R1, R2, and R3 primarily due to their lower temperature coefficient, which helps maintain the relative stability between resistors, thus influencing the temperature characteristics of the Bandgap. Resistor ratio matching is also particularly crucial in the design.

Design Challenges and Observations:​

• Common Centroid and Temperature Drift: It is challenging to minimize temperature drift while maintaining a Common Centroid layout for the resistors. I found it difficult to balance these two goals simultaneously and have not yet found the sweet spot to achieve a very low temperature coefficient.
• Poor PSRR Performance (5.5V): The PSRR (Power Supply Rejection Ratio) of the circuit is not as expected (-46.6dB) at a 5.5V supply voltage. I have tried to identify which part causes the PSRR drop but haven't fully clarified it. This is something I need to re-examine and analyze in detail.

Areas for Expected Feedback:​

I would particularly appreciate questions and suggestions from everyone regarding the following aspects:

• Circuit stability analysis
• Consideration and optimization of component sizes
• Power optimization techniques
• Noise analysis and suppression techniques
• Potential issues or areas for improvement in the design
• Key conceptual questions interviewers might focus on

Thank you again for your enthusiastic participation and time! I look forward to exchanging ideas with you!​

 

[dick_freebird]

If you want to sound experienced you might discuss things
like curvature and how it relates to specific resistor choice;
how to attain production accuracy across PVTM (trimming);
your startup needs to be more than a rectangle saying so.
You could discuss what "corners" or device qualities make
startup most difficult.

You could choose to contrast with the simpler style of
PTAT-mirror-loop (no op amp, just transimpedance voltage
gain and direct feedback) in various performance dimensions.

You could discuss challenges in reference design for low
supply voltages, HF PSRR as a care-about in modern high
integration chip design or chips powered by switching
regulators.