"Time" as a search parameter is not helpful since all MOSFETs between different manufacturers are tested at different operating conditions. Even MOSFETs from same manufacturer but different technology is tested with different conditions.according to its switching speed
No prob for any usual MOSFET driver
If everything is okay for nothing,because the power is consumed in the load.May I ask why it needs that high power rating?
if you look into the datasheet for PD = 170W, then this means continous power dissipation.the transistor to survive 170W PD for time 10ms.
Again, can you see that they are tested at different conditions ? In other words, switching times manufacturers give are note comparable.td(off) 66ns 400V 8.1A IXFH12N50F 28ns for 250V 6A
Why ?
Sure it matches.I see about 3W for DC at 25°C as well as 80° Tc
I see about 9W for 10ms at 25°C as well as 80° Tc
Both SOA values do not match the Power dissipation chart, which shows about 90W at 25°C and 50W at 80°C.
(80°C - 25°C) / (90W -50W) = 1.375K/W which almost perfectly meets the 1.36K/W given in the datsheet for R_th_JC.
Sure it matches.
The SOA curve starts to be power limited (at DC) at the same value the Power dissipation graph (Diagram 1 shows).
Diagram 2 (Tc=25ÂşC):
The graph starts to be limited at about ~18V*5A~90 W <<-- same as Diagram 1 shows.
Diagram 3 (Tc=80ÂşC):
The graph starts to be limited at about ~13V*4A~52 W <<-- same as Diagram 1 shows.
Thanks for this information. I didnt know about this effect.switching power mosfets have a little discussed failure mechanism as the Vds goes up, under linear operation, esp above 100VDC. A google search will likely provide some papers on the matter.
Like Peasy said, for the DC case in that SOA chart, the line they are plotting is in linear operating mode (i.e. saturation region). It is not limited by the thermal dissipation. The thermal dissipation limit line appears a bit in the 10ms case and increases as the pulses gets shorter.Let´s say 90W... and for my understanding it should not matter if the 90W come from 18V*5A or 18A*5V....but the chart says: it matters.
Here the IPW60R125CFD7 SOA chart.
In linear mode operation, there is a risk of getting hot spots at low gate-source voltages due to thermal run away. This effect becomes more important for latest trench technologies with high current densities, where the “zero temperature coefficient” point of the transfer characteristic is shifted to higher drain
currents. More information can be found in the application note mentioned above "Linear Mode Operation and Safe Operating Diagram of Power MOSFETs"
Yes, I wrote it wrong.You wrote: 18V*5A --> but you meant: 18A*5V.
is note quite the same thing, a device can be operating in a linear mode, but far from saturation.linear operating mode (i.e. saturation region)
Seems to me that you are calling linear mode to the ohmic region, which seems contradictory to the 60VDS you have ? Otherwise, in your view you have 4 operating modes of a FET (cutoff, ohmic, xx, saturation).is note quite the same thing, a device can be operating in a linear mode, but far from saturation.
What "Vgs" do you use ?often the fets are conducting 780mA at 60VDc applied ( i.e 47W per fet / TO-247 ) but are far from saturated
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