SDRAM CAS latency query

[explorick]

In SDRAM CAS latency will be generally 2 or 3. Why it cant be one? Why devices with CAS latency=3 have higher operating speeds compared to CAS latency=2 devices?

 

[FvM]

Simply assume a specific absolute amount of time required to activate a memory column.

 

[camr]

It takes a minimum amount of time (regardless of clock speed) to execute the retrieval of data from the memory array inside an SDRAM, and put its result onto the output pins. At the heart it is a very analog operation, and the time needed does not improve as quickly with advances in CMOS technology, because of increasing storage density (smaller capacitors and wires), limited power budgets, etc. If there are no devices with CAS latency of 1, it is because at the spec operating frequency, one clock cycle is just not enough time for things to happen. Similarly, setting the CAS latency to a higher value is a trade-off that allows you to run the clock faster by agreeing to wait one more clock cycle for your results.

 

[embeddedlover]

If in our spec if it is mentioned DDR-667 has CAS latency of 2, it implies at 333MHz it is 2. how to determine CAS latency if i operate the module at 200MHz?

---------- Post added at 18:10 ---------- Previous post was at 18:05 ----------

I have got another good explanation of CAS latency which is easily understandable, "chip set accesses the ROW of the memory matrix by putting an address on the memory's address pins and activating the RAS signal. Then, we have to wait a few clock cycles (known as RAS-to-CAS Delay). Then, the column address is put on the address pins, and the CAS signal is activated, to access the correct COLUMN of the memory matrix. Then, we wait a few clock cycles before data appears on output pin..this number of cycles is known as CAS latency"

 

[camr]

In my experience, the specification for a memory module should specify the max datarate / clock rate at which each of the latency settings is supported. You should not assume the chip can hit its max datarate at all of its latencies; the shorter latencies often require slower operation.