It takes a minimum amount of time (regardless of clock speed) to execute the retrieval of data from the memory array inside an SDRAM, and put its result onto the output pins. At the heart it is a very analog operation, and the time needed does not improve as quickly with advances in CMOS technology, because of increasing storage density (smaller capacitors and wires), limited power budgets, etc. If there are no devices with CAS latency of 1, it is because at the spec operating frequency, one clock cycle is just not enough time for things to happen. Similarly, setting the CAS latency to a higher value is a trade-off that allows you to run the clock faster by agreeing to wait one more clock cycle for your results.