petroka
Newbie level 3

Hi all,
I am currently having some problems in the annotation of the SDF file on the post-synthesis verilog netlist using VCS by Synopsys. Despite of all of those warnings the simulation goes on, but I am not really sure if all the timing are really annotated!
I would like to know from you if I really have to take care of such warnings or not and if it is possible to fix them!
Sorry to have attached so match code next but I think it is really necessary!
Thank you really match for the help!
The warning are of the following type (they are many!):
Warning-[SDFCOM_INF] IOPATH not found
top_cpa_dyn52@0.02ns.sdf, 1410
module: ENSVTX4, "instance: tb_top_cpa_dyn52b.UUT.U520"
SDF Warning: IOPATH from A to Z is not found.
Where the SDF 1410th line is (the cell is a two input exclusive nor):
(CELL
(CELLTYPE "ENSVTX4")
(INSTANCE U520)
(DELAY
(ABSOLUTE
(COND !B (IOPATH A Z (0.058:0.058:0.058) (0.060:0.060:0.060)))
(COND B (IOPATH A Z (0.042:0.042:0.042) (0.058:0.059:0.059)))
(IOPATH (posedge A) Z (0.058:0.058:0.058) (0.062:0.062:0.062)) // 1410th of SDF file
(IOPATH (negedge A) Z (0.058:0.058:0.058) (0.061:0.062:0.062))
(COND !A (IOPATH B Z (0.045:0.047:0.047) (0.050:0.052:0.052)))
(COND A (IOPATH B Z (0.036:0.038:0.038) (0.049:0.051:0.051)))
(IOPATH (posedge B) Z (0.049:0.051:0.051) (0.053:0.055:0.055))
(IOPATH (negedge B) Z (0.045:0.047:0.047) (0.049:0.051:0.051))
)
)
---------------------------------------------------------------------------------------------
While the verilog library of the cell is characterized by:
// START
// CELL ENSVTX4
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
`ifdef functional
`timescale 1ns / 1ns
`delay_mode_zero
`else
`timescale 1ns / 1ps
`delay_mode_path
`endif
`define ENSVTX4_B_F_Z_F 0.1
`define ENSVTX4_B_R_Z_R 0.1
`define ENSVTX4_B_F_Z_R 0.1
`define ENSVTX4_B_R_Z_F 0.1
`define ENSVTX4_A_F_Z_F 0.1
`define ENSVTX4_A_R_Z_R 0.1
`define ENSVTX4_A_F_Z_R 0.1
`define ENSVTX4_A_R_Z_F 0.1
module ENSVTX4 (Z, A, B);
output Z;
input A;
input B;
xnor #1 u0 (Z, A, B);
`ifdef functional
`else
specify
if (A) (B +=> Z) = (`ENSVTX4_B_R_Z_R,`ENSVTX4_B_F_Z_F); // there are only 4 if statement!
if (!A) (B -=> Z) = (`ENSVTX4_B_F_Z_R,`ENSVTX4_B_R_Z_F);
if (B) (A +=> Z) = (`ENSVTX4_A_R_Z_R,`ENSVTX4_A_F_Z_F);
if (!B) (A -=> Z) = (`ENSVTX4_A_F_Z_R,`ENSVTX4_A_R_Z_F);
endspecify
`endif
endmodule // ENSVTX4
`ifdef verifault
`disable_portfaults
`nosuppress_faults
`endif
`endcelldefine
// END
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Some other warning are genearated for the memory cells as well:
Warning-[SDFCOM_CFTC] Cannot find timing check
RNSFIR-post_syn.sdf, 1466382
module: FD2QSVTX2, "instance: E.UUT.\fir_19/rey_051/z_reg[0] "
SDF Warning: Cannot find timing check $hold(posedge CP,posedge CD,...)
The memory cell SDF is as follow:
(CELL
(CELLTYPE "FD2QSVTX2")
(INSTANCE fir_19\/rey_051\/z_reg\[0\])
(DELAY
(ABSOLUTE
(IOPATH (posedge CP) Q (0.074411:0.074411:0.074411) (0.094720:0.094720:0.094720))
(IOPATH (negedge CD) Q () (0.107344:0.107344:0.107344))
)
)
(TIMINGCHECK
(WIDTH (posedge CP) (0.070000:0.070000:0.070000))
(WIDTH (negedge CP) (0.120000:0.120000:0.120000))
(HOLD (posedge CD) (posedge CP) (-0.000166:-0.000166:-0.000166)) <-- The line 1466382
(RECOVERY (posedge CD) (posedge CP) (0.075275:0.075275:0.075275))
(HOLD (posedge D) (posedge CP) (-0.031501:-0.035651:-0.035651))
(HOLD (negedge D) (posedge CP) (-0.014575:-0.017560:-0.017560))
(SETUP (posedge D) (posedge CP) (0.086892:0.091038:0.091038))
(SETUP (negedge D) (posedge CP) (0.065168:0.068504:0.068504))
(WIDTH (negedge CD) (0.105000:0.105000:0.105000))
)
)
The memory cell verilog library is as follow:
// START
// CELL FD2QSVTX2
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
`ifdef functional
`timescale 1ns / 1ns
`delay_mode_unit
`else
`timescale 1ns / 1ps
`delay_mode_path
`endif
`define FD2QSVTX2_CD_F_Q_F 0.1
`define FD2QSVTX2_CP_R_Q_R 0.1
`define FD2QSVTX2_CP_R_Q_F 0.1
`define FD2QSVTX2_D_CP_HOLD_posedge_posedge 0.1
`define FD2QSVTX2_D_CP_HOLD_negedge_posedge 0.1
`define FD2QSVTX2_D_CP_SETUP_posedge_posedge 0.1
`define FD2QSVTX2_D_CP_SETUP_negedge_posedge 0.1
`define FD2QSVTX2_CP_PWL 0.1
`define FD2QSVTX2_CP_PWH 0.1
`define FD2QSVTX2_CD_PWL 0.1
`define FD2QSVTX2_CD_CP_REC_posedge_posedge 0.1
`define FD2QSVTX2_CD_CP_REM_posedge_posedge 0.1
module FD2QSVTX2 (Q, D, CP, CD);
output Q;
input D;
input CP;
input CD;
`ifdef functional
reg Notifier;
U_FD_P_RN_NOTI u0 (IQ, D, CP, CD, Notifier);
buf #1 u1 (Q, IQ);
`else
reg Notifier;
U_FD_P_RN_NOTI u0 (IQ, dD, dCP, dCD, Notifier);
buf #1 u1 (Q, IQ);
specify
`ifdef verifault
if(CD) (posedge CP => (Q +: D)) = (`FD2QSVTX2_CP_R_Q_R, `FD2QSVTX2_CP_R_Q_F);
(negedge CD => (Q +: 1'b0)) = (`FD2QSVTX2_CD_F_Q_F,`FD2QSVTX2_CD_F_Q_F);
$setuphold(posedge CP &&&CD, posedge D, `FD2QSVTX2_D_CP_SETUP_posedge_posedge, `FD2QSVTX2_D_CP_HOLD_posedge_posedge, Notifier);
$setuphold(posedge CP &&& CD, negedge D, `FD2QSVTX2_D_CP_SETUP_negedge_posedge, `FD2QSVTX2_D_CP_HOLD_negedge_posedge, Notifier);
$width(negedge CP, `FD2QSVTX2_CP_PWL, 0, Notifier);
$width(posedge CP &&& CD, `FD2QSVTX2_CP_PWH, 0, Notifier);
$width(negedge CD, `FD2QSVTX2_CD_PWL, 0, Notifier);
$recovery(posedge CD, posedge CP &&& D, `FD2QSVTX2_CD_CP_REC_posedge_posedge, Notifier);
$hold(posedge CP &&& D, posedge CD, `FD2QSVTX2_CD_CP_REM_posedge_posedge, Notifier);
`else
(posedge CP => (Q +: D)) = (`FD2QSVTX2_CP_R_Q_R, `FD2QSVTX2_CP_R_Q_F);
(negedge CD => (Q +: 1'b0)) = (`FD2QSVTX2_CD_F_Q_F,`FD2QSVTX2_CD_F_Q_F);
$setuphold(posedge CP , posedge D, `FD2QSVTX2_D_CP_SETUP_posedge_posedge, `FD2QSVTX2_D_CP_HOLD_posedge_posedge, Notifier,,dCD,dCP,dD);
$setuphold(posedge CP , negedge D, `FD2QSVTX2_D_CP_SETUP_negedge_posedge, `FD2QSVTX2_D_CP_HOLD_negedge_posedge, Notifier,,dCD,dCP,dD);
$width(negedge CP, `FD2QSVTX2_CP_PWL, 0, Notifier);
$width(posedge CP &&& CD, `FD2QSVTX2_CP_PWH, 0, Notifier);
$width(negedge CD, `FD2QSVTX2_CD_PWL, 0, Notifier);
$recrem(posedge CD, posedge CP , `FD2QSVTX2_CD_CP_REC_posedge_posedge,`FD2QSVTX2_CD_CP_REM_posedge_posedge, Notifier,,dD,dCD,dCP);
`endif
endspecify
`endif
endmodule // FD2QSVTX2
`ifdef verifault
`disable_portfaults
`nosuppress_faults
`endif
`endcelldefine
I am currently having some problems in the annotation of the SDF file on the post-synthesis verilog netlist using VCS by Synopsys. Despite of all of those warnings the simulation goes on, but I am not really sure if all the timing are really annotated!
I would like to know from you if I really have to take care of such warnings or not and if it is possible to fix them!
Sorry to have attached so match code next but I think it is really necessary!
Thank you really match for the help!
The warning are of the following type (they are many!):
Warning-[SDFCOM_INF] IOPATH not found
top_cpa_dyn52@0.02ns.sdf, 1410
module: ENSVTX4, "instance: tb_top_cpa_dyn52b.UUT.U520"
SDF Warning: IOPATH from A to Z is not found.
Where the SDF 1410th line is (the cell is a two input exclusive nor):
(CELL
(CELLTYPE "ENSVTX4")
(INSTANCE U520)
(DELAY
(ABSOLUTE
(COND !B (IOPATH A Z (0.058:0.058:0.058) (0.060:0.060:0.060)))
(COND B (IOPATH A Z (0.042:0.042:0.042) (0.058:0.059:0.059)))
(IOPATH (posedge A) Z (0.058:0.058:0.058) (0.062:0.062:0.062)) // 1410th of SDF file
(IOPATH (negedge A) Z (0.058:0.058:0.058) (0.061:0.062:0.062))
(COND !A (IOPATH B Z (0.045:0.047:0.047) (0.050:0.052:0.052)))
(COND A (IOPATH B Z (0.036:0.038:0.038) (0.049:0.051:0.051)))
(IOPATH (posedge B) Z (0.049:0.051:0.051) (0.053:0.055:0.055))
(IOPATH (negedge B) Z (0.045:0.047:0.047) (0.049:0.051:0.051))
)
)
---------------------------------------------------------------------------------------------
While the verilog library of the cell is characterized by:
// START
// CELL ENSVTX4
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
`ifdef functional
`timescale 1ns / 1ns
`delay_mode_zero
`else
`timescale 1ns / 1ps
`delay_mode_path
`endif
`define ENSVTX4_B_F_Z_F 0.1
`define ENSVTX4_B_R_Z_R 0.1
`define ENSVTX4_B_F_Z_R 0.1
`define ENSVTX4_B_R_Z_F 0.1
`define ENSVTX4_A_F_Z_F 0.1
`define ENSVTX4_A_R_Z_R 0.1
`define ENSVTX4_A_F_Z_R 0.1
`define ENSVTX4_A_R_Z_F 0.1
module ENSVTX4 (Z, A, B);
output Z;
input A;
input B;
xnor #1 u0 (Z, A, B);
`ifdef functional
`else
specify
if (A) (B +=> Z) = (`ENSVTX4_B_R_Z_R,`ENSVTX4_B_F_Z_F); // there are only 4 if statement!
if (!A) (B -=> Z) = (`ENSVTX4_B_F_Z_R,`ENSVTX4_B_R_Z_F);
if (B) (A +=> Z) = (`ENSVTX4_A_R_Z_R,`ENSVTX4_A_F_Z_F);
if (!B) (A -=> Z) = (`ENSVTX4_A_F_Z_R,`ENSVTX4_A_R_Z_F);
endspecify
`endif
endmodule // ENSVTX4
`ifdef verifault
`disable_portfaults
`nosuppress_faults
`endif
`endcelldefine
// END
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Some other warning are genearated for the memory cells as well:
Warning-[SDFCOM_CFTC] Cannot find timing check
RNSFIR-post_syn.sdf, 1466382
module: FD2QSVTX2, "instance: E.UUT.\fir_19/rey_051/z_reg[0] "
SDF Warning: Cannot find timing check $hold(posedge CP,posedge CD,...)
The memory cell SDF is as follow:
(CELL
(CELLTYPE "FD2QSVTX2")
(INSTANCE fir_19\/rey_051\/z_reg\[0\])
(DELAY
(ABSOLUTE
(IOPATH (posedge CP) Q (0.074411:0.074411:0.074411) (0.094720:0.094720:0.094720))
(IOPATH (negedge CD) Q () (0.107344:0.107344:0.107344))
)
)
(TIMINGCHECK
(WIDTH (posedge CP) (0.070000:0.070000:0.070000))
(WIDTH (negedge CP) (0.120000:0.120000:0.120000))
(HOLD (posedge CD) (posedge CP) (-0.000166:-0.000166:-0.000166)) <-- The line 1466382
(RECOVERY (posedge CD) (posedge CP) (0.075275:0.075275:0.075275))
(HOLD (posedge D) (posedge CP) (-0.031501:-0.035651:-0.035651))
(HOLD (negedge D) (posedge CP) (-0.014575:-0.017560:-0.017560))
(SETUP (posedge D) (posedge CP) (0.086892:0.091038:0.091038))
(SETUP (negedge D) (posedge CP) (0.065168:0.068504:0.068504))
(WIDTH (negedge CD) (0.105000:0.105000:0.105000))
)
)
The memory cell verilog library is as follow:
// START
// CELL FD2QSVTX2
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
`ifdef functional
`timescale 1ns / 1ns
`delay_mode_unit
`else
`timescale 1ns / 1ps
`delay_mode_path
`endif
`define FD2QSVTX2_CD_F_Q_F 0.1
`define FD2QSVTX2_CP_R_Q_R 0.1
`define FD2QSVTX2_CP_R_Q_F 0.1
`define FD2QSVTX2_D_CP_HOLD_posedge_posedge 0.1
`define FD2QSVTX2_D_CP_HOLD_negedge_posedge 0.1
`define FD2QSVTX2_D_CP_SETUP_posedge_posedge 0.1
`define FD2QSVTX2_D_CP_SETUP_negedge_posedge 0.1
`define FD2QSVTX2_CP_PWL 0.1
`define FD2QSVTX2_CP_PWH 0.1
`define FD2QSVTX2_CD_PWL 0.1
`define FD2QSVTX2_CD_CP_REC_posedge_posedge 0.1
`define FD2QSVTX2_CD_CP_REM_posedge_posedge 0.1
module FD2QSVTX2 (Q, D, CP, CD);
output Q;
input D;
input CP;
input CD;
`ifdef functional
reg Notifier;
U_FD_P_RN_NOTI u0 (IQ, D, CP, CD, Notifier);
buf #1 u1 (Q, IQ);
`else
reg Notifier;
U_FD_P_RN_NOTI u0 (IQ, dD, dCP, dCD, Notifier);
buf #1 u1 (Q, IQ);
specify
`ifdef verifault
if(CD) (posedge CP => (Q +: D)) = (`FD2QSVTX2_CP_R_Q_R, `FD2QSVTX2_CP_R_Q_F);
(negedge CD => (Q +: 1'b0)) = (`FD2QSVTX2_CD_F_Q_F,`FD2QSVTX2_CD_F_Q_F);
$setuphold(posedge CP &&&CD, posedge D, `FD2QSVTX2_D_CP_SETUP_posedge_posedge, `FD2QSVTX2_D_CP_HOLD_posedge_posedge, Notifier);
$setuphold(posedge CP &&& CD, negedge D, `FD2QSVTX2_D_CP_SETUP_negedge_posedge, `FD2QSVTX2_D_CP_HOLD_negedge_posedge, Notifier);
$width(negedge CP, `FD2QSVTX2_CP_PWL, 0, Notifier);
$width(posedge CP &&& CD, `FD2QSVTX2_CP_PWH, 0, Notifier);
$width(negedge CD, `FD2QSVTX2_CD_PWL, 0, Notifier);
$recovery(posedge CD, posedge CP &&& D, `FD2QSVTX2_CD_CP_REC_posedge_posedge, Notifier);
$hold(posedge CP &&& D, posedge CD, `FD2QSVTX2_CD_CP_REM_posedge_posedge, Notifier);
`else
(posedge CP => (Q +: D)) = (`FD2QSVTX2_CP_R_Q_R, `FD2QSVTX2_CP_R_Q_F);
(negedge CD => (Q +: 1'b0)) = (`FD2QSVTX2_CD_F_Q_F,`FD2QSVTX2_CD_F_Q_F);
$setuphold(posedge CP , posedge D, `FD2QSVTX2_D_CP_SETUP_posedge_posedge, `FD2QSVTX2_D_CP_HOLD_posedge_posedge, Notifier,,dCD,dCP,dD);
$setuphold(posedge CP , negedge D, `FD2QSVTX2_D_CP_SETUP_negedge_posedge, `FD2QSVTX2_D_CP_HOLD_negedge_posedge, Notifier,,dCD,dCP,dD);
$width(negedge CP, `FD2QSVTX2_CP_PWL, 0, Notifier);
$width(posedge CP &&& CD, `FD2QSVTX2_CP_PWH, 0, Notifier);
$width(negedge CD, `FD2QSVTX2_CD_PWL, 0, Notifier);
$recrem(posedge CD, posedge CP , `FD2QSVTX2_CD_CP_REC_posedge_posedge,`FD2QSVTX2_CD_CP_REM_posedge_posedge, Notifier,,dD,dCD,dCP);
`endif
endspecify
`endif
endmodule // FD2QSVTX2
`ifdef verifault
`disable_portfaults
`nosuppress_faults
`endif
`endcelldefine