SDF Back annotation Problem

[tatonki1]

sdf back annotation

I'm trying to backannotate SDF into a compiled ROM. The verilog for this ROM has the following timing variable: $setuphold. The SDF out of primetime has $SETUP and $HOLD. When I run ncverilog I get a bunch of the following errors:

ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (SETUP (posedge CEN) (posedge CLK) (0.282)) of instance rom256x18_id of module rom256x18_id <../rom256.sdf.new, line 44>.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (SETUP (negedge CEN) (posedge CLK) (0.282)) of instance rom256x18_id of module rom256x18_id <../rom256.sdf.new, line 45>.


The compiler vendor claims there is nothing wrong, but I am skeptical. For back annotation to work, do the timing variables have to be the same in the verilog and sdf files? Or is there a switch I can set in either ncverilog when I run the sim, or PT when I dump out the sdf so as to match up the timing variable in verilog to $setuphold???

Thanks for any responses...I'm stuck here.
Rgds,
-c

 

[FLEXcertifydll]

sdf backannotation

perhaps there is little diff between the sim library and the STA library.

 

[Arturi]

sdf back annotate

Hi there,

I am sure you can set a switch in PT to generate the timing constraints of the SDF file in "setuphold" format instead of split "setup" and "hold" statements.

Are you sure you are not compiling the memories with some switch that disable time checking? Like +notimecheks or something? If you are compiling with such a switch then the elaboration will fail to backannotate the timing to the memory.

hope it helps

cheers

 

[aji_vlsi]

timing sdf back annotation

I'm trying to backannotate SDF into a compiled ROM. The verilog for this ROM has the following timing variable: $setuphold. The SDF out of primetime has $SETUP and $HOLD. When I run ncverilog I get a bunch of the following errors:

I'm sure that PT has a way to write a combined SETUPHOLD check though I did not check it myself. But usually simulators allow this well, I believe Modelsim will do this by default, VCS needs +create_setuphold (or something similar) flag. Not sure of NC.

The compiler vendor claims there is nothing wrong, but I am skeptical.

Good you are, I would be cautious as well.

HTH
Ajeetha, CVC
www.noveldv.com