sdf annotation problem

[umairsiddiqui]

Hi
I'm trying to synthesize a design (leon3) in ST-65 nm.

The design is already tested in other technology and In this case I just ported the memories blocks (caches) and pads to new technology.

In 65nm, The design is running is correctly in functional simulation but it is not working 65 nm. One issue I found is SDF annotation,

When I generate the SDF from Design compiler, I get SDF many warnings in Model sim
of type 3261

# ** Warning: (vsim-SDF-3261) /tmp/umair/grlib-gpl-1.0.22-b4095/designs/leon3-stm65/synopsys/leon3mp.sdf(1069361): Failed to find matching specify module path.


verror 3261 reveled that

# vsim Message # 3261:
# No module path in a specify block in the related module instance was
# found to match the SDF construct on the specified line. Verify that
# the SDF file is being applied to the correct design instance and that
# a specify block exists in this module instance and contains the
# appropriate module path. If a COND is being used, verify that the order
# of the condition is the same in the specify block as it is in the
# SDF file.
#

The memory model user guide from ST says that I need to use some mapping files
while writting the SDF

For performing STA, a separate mapping file (<library>_pt.map) is present which is used to write a sdf file. Timing Analysis, should be performed by reading this sdf in primetime shell.
An example of using a mapping file for writing SDF using a mapping file is can be

write_sdf -map SPHS.map -output SPHS.sdf

The above command writes out a SDF "SPHS.sdf" using the mapping file "SPHS.map".

now the write_sdf of design compiler doesn't support -map option

could any body please tell me how to proceed .
I tried to write a primetime script to write a new SDF file to use mapping file.

set link_library "[glob ./*.db] $link_library"
set target_library "[glob ./*.db] $target_library"

# reading the netlist from DC 
read_verilog ./synopsys/leon3mp.v

current_design leon3mp
create_clock -name "clka" -period 20 clka

write_sdf -map ../../lib/tech/stm65/mem/SPHS100823.verilog.map -context verilog -output leon3mp.sdf

report_disable_timing > timing_disable_report

This is however not working....The warning of type 3262 is removed
instead a new type of SDF warning is generated by modelsim 3259.

# ** Warning: (vsim-SDF-3259) (null)(4905102): Invalid ports for INTERCONNECT.

by

verr 3259 in modelsim i got following message:

vsim Message # 3259:
# The first port instance in an INTERCONNECT entry must be an output
# or bidirectional port. The second port instance must be an input
# or bidirectional port.
# [DOC: OVI Standard Delay Format Specification v3.0 -
# Chapter 3, Section: Delay Definition Entries (page 3-22)]


The design is completely flattened.

 

[nsingh95]

Hi Uma,
Two things:

1st : I think your design is in VHDL.So, please check whether a component of the module is declared or not in the file. i.e.

suppose your design has cachemem.vhd [/B]which has an instance of memory i.e. dpram : inst (a;;''''''''').....

So please check whether the component of dpram module is present in cachemem or not.If not then please add it. It will not show that error.

2nd : Please do include the memory models in the file list for synthesis. THe tool will itself search it.But while simulation please do include it.
I think if u do this your issue will be resolved.If I am right u r using Synopsys DC.

 

[umairsiddiqui]

Hi,
thanks for the reply. I followed the guidelines written in GRLIB User's Manual. The section 9.5 of this manual discuss adding support for new target technologies.

I have declared the memory components...my file is very similar to attached. i don't have the actual file right now, in which i have instantiated the ST memories. but i used the attached code as a reference.