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SDF annotation problem in asynch flip-flops

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ebrahimi.khoy

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Hi,

I want to do post-synth simulation on a processor. Now, I am working on SDF annotation. SDF file is created by design compiler and it is read by modelsim. During read there is no problem for combinational elements, but I got lots of warnings for asynchronous flipflops indicating it cannot match some constraints/paths. I have checked in the SDF file and the erronous lines are either timing constants (Setup/hold/... time) or conditional paths in flip-flops.

Any idea to solve this problem?
 
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The timing arcs are not okay in the .libs. Please check the .lib and also the timing information in the verilog timing database.
ebrahimi.khoy said:
Hi,

I want to do post-synth simulation on a processor. Now, I am working on SDF annotation. SDF file is created by design compiler and it is read by modelsim. During read there is no problem for combinational elements, but I got lots of warnings for asynchronous flipflops indicating it cannot match some constraints/paths. I have checked in the SDF file and the erronous lines are either timing constants (Setup/hold/... time) or conditional paths in flip-flops.

Any idea to solve this problem?
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