# sdf annotate question

Status
Not open for further replies.

#### lightcloud

##### Member level 4
sdf annotate

Hi,
when I annotate sdf in ncverilog,I found all interconnect can be annotated
,but the cell delay cannot annotated,it report failed to identify IOPATH A,Y
in xxxxxxxxxx instancexxxx?Can tell me why?there is a explanation in doccument
that the library has no timing path of the cell.how to check it?

thanks a lot

#### aji_vlsi

ncsdfc

lightcloud said:
Hi,
when I annotate sdf in ncverilog,I found all interconnect can be annotated
,but the cell delay cannot annotated,it report failed to identify IOPATH A,Y
in xxxxxxxxxx instancexxxx?Can tell me why?there is a explanation in doccument
that the library has no timing path of the cell.how to check it?

thanks a lot

In your netlist, check that there is a valid path from A to Y in the specified instance. If you show the exact error message from the tool, I can help you more. BTW, which tool & version are you using? Specify that as well.

Ajeetha, CVC
www.noveldv.com

#### ram

+sdf_file

Hi ,

I f you r u using cadence tools here is a very simple procedure for timmng simulation -

1. Copy the .sdf file in the folder from where you are invoking the commands
2. Use -autosdf switch in ncelab
3. If your testbench (where netlist is instantiated) is in verilog use initialise to call sdf file.
4. If your testbench is in VHDL you dont need to specify the sdf file name.

All old procedures like using ncsdfc, or creating command file of SDF is not required if your use -autosdf.

Hope this helps you.

Regards,
Ramchandra
NXP Semi.

#### aji_vlsi

verilog sdf_annotate corner

Hi Ram,
Few questions on your interesting -autosdf recommendation, please see if you can explain.

ram said:
Hi ,

I f you r u using cadence tools here is a very simple procedure for timmng simulation -

1. Copy the .sdf file in the folder from where you are invoking the commands

Why do we need to do that? As you would know, for large SoCs, the SDF can be 100s of MB (or even more), it doesn't look feasible. I've used CDN tools a lot in the past during my PSL book etc. Never it was required. Maybe we can do

Code:
  ncelab -autosdf /path/to/sdf_file.sdf

2. Use -autosdf switch in ncelab

All old procedures like using ncsdfc, or creating command file of SDF is not required if your use -autosdf.

Can you explain this switch in detail? Looks interesting. How would you choose whether user needs MIN/TYP/MAX corner in SDF file? What about annotation scope?

3. If your testbench (where netlist is instantiated) is in verilog use initialise to call sdf file.

Do you mean "initial" block? What's "initialise"?

4. If your testbench is in VHDL you dont need to specify the sdf file name.

Hope this helps you.

Regards,
Ramchandra
NXP Semi.

Then in VHDL how does it know the SDF file name?

Thanks
Ajeetha, CVC
www.noveldv.com

#### ram

$sdfannotate ncsim Hi Ajeetha, I have found following information in xilinx website ---- ---------------------------------------------------------------------------------------------- How do I back-annotate the SDF file for timing simulation using NC-Verilog? Solution 1: There are two methods for back-annotating delay values from an SDF file: 1. Compiling the SDF file at elaboration-time 2. Compiling the SDF file with NCSDFC The NC-Verilog simulator only reads compiled SDF files; the SDF source file is supplied as an argument in a$sdf_annotate task by NetGen.

To compile the SDF file at elaboration-time:

Use the -autosdf option:

ncelab -autosdf <testfixture_name> glbl

The elaborator first determines if the $sdf_annotate argument is an SDF file or a compiled file. If it determines that it is an SDF file, it then looks for a corresponding compiled file ("sdf_filename.X"). If it doesn't find a corresponding compiled file, the elaborator issues a warning message and then spawns the NCSDFC utility to automatically compile the SDF file. If a compiled file exists, NCSDFC checks to make sure that the date of the compiled file is newer than the date of the source file and that the version of the compiled file matches the version of NCSDFC. If either check fails, the SDF file is recompiled. Otherwise, the compiled file is simply read. When invoked by the elaborator, the NCSDFC utility generates a log file called "sdf_filename.log". Solution 2: To read the ASCII SDF file using the NCSDFC utility: SDF files must be with NCSDFC to annotate the timing information contained in the SDF file: ncsdfc sdf_filename.sdf NCSDFC will create a file called "sdf_filename.sdf.X". If a compiled file exists, NCSDFC checks to make sure that the date of the compiled file is newer than the date of the source file and that the version of the compiled file matches the version of NCSDFC. If either check fails, the SDF file is recompiled. Otherwise, the compiled file is simply read. ---------------------------------------------------------------------------------------------- I used above and tried the netlist simulation. About your VHDL question -- My test bench is in vhdl . The name of SDF file is same as the design name. I dont know whether the compiler will search for same name. When i tried above suggested procedure. It worked for me. However my colleague was tring the same & figured that it is not working. I investegated it. I found that he is using verilog testbench. So we tried the Initial statement to tell about which sdf file is to be used for which netlist. Then it worked. Hopw this helps, Ramchandra #### chandhramohan ##### Member level 2 sdf annotate in vhdl Hi , For ncverilog if your sdf file has min/max/typ corners then use either +mindelay or +maxdelay switch in compile options to chk WC , BC . Or else u can specify in the testbench along with$sdfannotate(filename , top ,min/max) .

Regards
Chandhramohan

Status
Not open for further replies.