SDC constraint inside Xilinx ISE

[promach]

Inside ISE timing constraint editor window, which following sub-section shall I use set_clock_group to solve the STA setup timing violation path #1 due to cross-clock signal ?

 

[dpaul]

@promach ,
I cannot help you out with your direct question, but I never use it. But I have an advise for you.

If possible write your constraints in a plain text editor and add it to the ISE/Vivado project as needed. Not only does this approach help you to understand the constraints better but this skill of independently writing the constraints will also help if you are using another FPGA tool-chain from another FPGA vendor.
It would also help you if in the future you decide to work for ASIC development flow.