Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

SDC: constraining same source, different frequency clocks, after mux

Status
Not open for further replies.

George_P

Member level 2
Joined
May 26, 2007
Messages
46
Helped
4
Reputation
8
Reaction score
3
Trophy points
1,288
Activity points
1,597
I have a master clock ("m_clk"), which is divided by 2 (using enable to a clk-gater), giving generated clock: "d2_clk".

Both clocks go to separate muxes, with different select (select is in the m_clk domain), giving generated clocks: "m1_clk" & "m2_clk".

Is there a way to constraint "m1_clk" & "m2_clk", so they can be used without metastability/sync concerns? I.e. so that each of them can consume data from the other clk domain, without CDC synchronization?
Or should I not even define "m1_clk" & "m2_clk" in the sdc, and only define mclk & d2_clk, and let the tool deal with the muxing?

I think that the tool may take care of this by default, because they are all generated clocks from the same source clk (since I have not false-pathed these clks). But I'm not certain due to the muxing.

Thank you
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top