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SDC: constraining same source, different frequency clocks, after mux

George_P

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I have a master clock ("m_clk"), which is divided by 2 (using enable to a clk-gater), giving generated clock: "d2_clk".

Both clocks go to separate muxes, with different select (select is in the m_clk domain), giving generated clocks: "m1_clk" & "m2_clk".

Is there a way to constraint "m1_clk" & "m2_clk", so they can be used without metastability/sync concerns? I.e. so that each of them can consume data from the other clk domain, without CDC synchronization?
Or should I not even define "m1_clk" & "m2_clk" in the sdc, and only define mclk & d2_clk, and let the tool deal with the muxing?

I think that the tool may take care of this by default, because they are all generated clocks from the same source clk (since I have not false-pathed these clks). But I'm not certain due to the muxing.

Thank you
 

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