Scope of variables and signals in VHDL and Verilog

[Dijskstra]

Hi all,


I know that in VHDL we can declare local variables like this:

process(clk, reset)
    variable v : integer;
begin
    if (reset = '1') then
       v := 0;
    elsif rising_edge(clk) then
       v := v + 1;
end process;

In the same way, can we declare local signals like the code below?

process(clk, reset)
    signal s : integer;
begin
    if (reset = '1') then
       s <= 0;
    elsif rising_edge(clk) then
       s <= s + 1;
end process;

And what about in Verilog?


Thank you

Anders

 

[vomit]

No, a signal declaration is only valid in a declarative context of a region containing parallel processes, such as a block or an entity.

In the declarative part of a process you can only declare sequential stuff such as variables, procedures, functions to be used in that process.

See signal_declaration in the BNF:
http://www.pldworld.com/_hdl/1/www.ireste.fr/fdl/vcl/lesd/Vbnf.htm

It makes sense because signals are mainly used to communicate between processes.

 

[dave_59]

To answer the Verilog part of this question, wires are defined in the declarative section of a module, just as signals are in VHDL. However, variables in Verilog may be defined the declarative or procedural section of your code.