Scope of jobs in verification

[jagz]

Hi,
Whats the scope of jobs in functional (RTL) verification in VLSI? From what I have heard from my friends and other people, verification jobs become kind of boring after a couple of years. Its just passing the test cases and verifying the RTL since the same environment can be used for different codes. Is this true? Also, I have heard people experienced in verification are trying to change the domain. I would like to know more on the prospects of taking up a job in verification. Kindly share your ideas and views on this.

Thanks

 

[Sckoarn]

jagz,
Verification is a good job compared with design. You get to use much more of a language for your job than RTL design, which is usually a limited set. As a verification person, you get to build everything that is NOT the RTL, which can be more chanllenging than the design itself. As a verification person, your focus is different from design. Your focus is proving functionality of the design, for the sake of quality. As in, the design works the way it is spec'ed to work. It can be very rewarding to find a bugs before they become hardware. Another thing is that, or the way it used to be, design seems to get the lime light, and verification is in the background. Things may have changed, but as a verification person, you are doing the work that most others do not want to do, you should always have a job.

Just some thoughts.
Sckoarn

 

[jagz]

jagz,
Verification is a good job compared with design. You get to use much more of a language for your job than RTL design, which is usually a limited set. As a verification person, you get to build everything that is NOT the RTL, which can be more chanllenging than the design itself. As a verification person, your focus is different from design. Your focus is proving functionality of the design, for the sake of quality. As in, the design works the way it is spec'ed to work. It can be very rewarding to find a bugs before they become hardware. Another thing is that, or the way it used to be, design seems to get the lime light, and verification is in the background. Things may have changed, but as a verification person, you are doing the work that most others do not want to do, you should always have a job.

Just some thoughts.
Sckoarn

Hi,
thanks for the info. However I would like to know a few more things. Will it be possible for a verification engineer to switch to RTL design afterwards?
Can verification engg go to the extend of becoming a project manager?
I have heard in India few verification engineers are switching to other domains like physical design etc, either because there are no quality projects or because they are fed up of the work they do. So on the long run will it be good?

Thanks in advance

 

[Sckoarn]

jagz,
If you want to be a designer, it is possible to transion from verification. But the language you use for verification will take you away from design consepts, namely SV. The longer you do pure verification, the more you will be seen as a verification person and less likely to get a job doing design.
A verification person can become a verification project manager, after some years of experience.

I try to automate the boring things and have fun with any new stuff. The job is what you make it. If you get on with a good team, your work can be very enjoyable as a verification person. Starting as a verification person and then moving into design, if you can, should make you a better designer, as you think slightly different. The quality of your designs should be better as you know how to test.

Sckoarn

 

[ljxpjpjljx]

if you want to become an verification engineer, you should be familar with VMM/OVM methodology!