aryajur
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I have attached the circuit diagram, the upper 2 PMOS transistors from the VDD line are M5 and M6 and the lower 2 NMOS from the gnd line are M2 and M1. The Transistors at the output are 2 NMOS M4 and M3 from the bottom.
A text says that the threshold when input is going from low to high is:
V+ = Vdd/(1+r) + Vthn/(1+r)
where r ~ √[(W2(L3+L4))/(W3,4 L2)]
and the threshold for input going high to low would be same as that of inverter given by:
V- = [r(VDD - Vthp) + Vthn]/(1+r) where r ~ √[(W5,6(L2+L1))/(W2,1 (L5 + L6))]
I can't get to these equations. Can anyone guide me?
A text says that the threshold when input is going from low to high is:
V+ = Vdd/(1+r) + Vthn/(1+r)
where r ~ √[(W2(L3+L4))/(W3,4 L2)]
and the threshold for input going high to low would be same as that of inverter given by:
V- = [r(VDD - Vthp) + Vthn]/(1+r) where r ~ √[(W5,6(L2+L1))/(W2,1 (L5 + L6))]
I can't get to these equations. Can anyone guide me?
