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Schematic Translator (EDIF -> ECS schemaitc)

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Full Member level 5
Apr 19, 2002
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In the topic <How to import gate-level netlist into ECS>,
elone Posted: 06 Oct 2002 18:45
elone said:
I use ECS241 , 446 for some years, I think your question will have no answer ! Think about millions gates netlist , in ecs , you must split it to thousands pages , it no possible !

I found there exists the tool for converting different schematic formats
at h**p://www.dataxpress.c0m/

If I have already written the gate-level netlist as the EDIF schematic by
$ynopsys' Des!gn C0mpiler, then I can use DXL102 to translate it into
ECS .sch format.

So instead of "If there exists the tool for schematic translator ?",
the question should be "Any one can share DataXpress' software ?"

Waiting for reply :eek:

Is this software working with Xilinx?

$ynario EC$ Schematic Entry

The relationship between several EDA tools.... :eek:

1. Synari0
X.i.|.i.n.x has discontinued selling $ynario EC$ !
ps: No new device support nor updates will be supplied by Xi|inx for these products.

2. X!linx and Cohesi0n
Xi|inx has licensed the schematic capture tool EC$ (Engineering Capture $ystem) to C.0.h.e.s.i.o.n S.y.s.t.e.m.s.

3. D@taXpress
EDI (D.a.t.a.X.p.r.e.s.s' database link) is an integration hub through which electronic design information passes between different EDA vendor databases or formats.

DXL1OO: EC$ Schematic Translator
DXL1OO Schematic Translator transfers schematic information both into and out of the Engineering Capture $ystem database. All data into and out of EC$ pass through the EDI database. It can then be transferred either directly to or from other EDA vendors (linked to the EDI database) or to or from any EDA vendor that has an EDIF schematic interface.

DXL15OO: Verilog Netlist Translator
DXL15OO Verilog Netlist Translator transfers structural Verilog information to and from EDI.
Thus, the DXL15OO provides a Verilog link to any EDA vendor database or format that is integrated with EDI. The Verilog information can also be output to an EDIF netlist file, or structural Verilog can be created by reading an EDIF netlist file.

Have anyone know ECS 6.0 ??

My friend said ECS 6.0(Cohession HDS) support Spice/verilog input --> schematic and can edit , spiceVisionalos read spice to schematic , but not support other netlist

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