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Schematic Simulation with Verilog XL

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tia_design

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I designed a traditional JK flip flop, the entry is schematic, and simulation is done by Verilog XL. I found that the output of such JK flop flop is undefined. I found the reason is that in this JK, the output is connected back to the input nmos, which is undefined when simulation is begun. Who can tell me how to avoid this? Thanks
 

eda_wiz

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Apply Reset while Intialising the Simulation
 

spauls

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Apply reset and check for all Input combinations.
 

marksile

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You can reset or set. you can add default to q and qn in testbench file also.
 

hover

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I have met same question when I first use the tool.
You must add a reset or set signal to the flip-flop in order to initialize it.
 

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