schematic from netlist

[jarillak]

Hi.................

How to import schematic from netlist in cadence.............?
Can anyone help me...........

 

[erikl]

How to import schematic from netlist in cadence.............?

If it's a SPICE netlist, see **broken link removed**. With a SPECTRE netlist, a similar method should work.

 

[jarillak]

Hi erikl..........

Ur reply is very helpful to me.............
I implemented the techniques to simple logic gates which has flat level MOSFETs.
When i used the same technique for large circuits with different instances,i can't achieve the result.
Is there any special steps to write devicemap file for circuits with different instances.
Could anybody help me.........

 

[erikl]

When i used the same technique for large circuits with different instances,i can't achieve the result.

Well, AFAIR this doesn't work well over hierarchies. Seems to be a problem of local/global node names which this method can't solve. Either you can solve the problem in the netlist by assigning unique node names, or you'd have to create individual schematics for each module in a hierarchy, then put these schematics together in a new schematic hierarchy.

Tedious, I know. But I don't know another way in such case.

 

[jarillak]

thanks for ur replies...........

 

[jarillak]

Hi..........


In schematic conversion from netlist, i got errors in resistor based circuits.
the error is,

(ERROR (AVLVSNN-10091) : 'rhrpo_3t_ckt' cell requested to blackbox could not be netlisted as no pin information is available.Check blackBoxPinInfo settings for the cell.
*ERROR* cell 'rhrpo_3t_ckt' is not defined.


[rhrpo_3t_ckt---->resistor name]
How can i overcome it....
And also after importing,the MOSFET were assigned with minimum dimensions.
Is there any specific code in devicemap file to specify the MOSFET size(length,width,multiplier).......??????

 

[erikl]

(ERROR (AVLVSNN-10091) : 'rhrpo_3t_ckt' cell requested to blackbox could not be netlisted as no pin information is available.Check blackBoxPinInfo settings for the cell.
*ERROR* cell 'rhrpo_3t_ckt' is not defined.
[rhrpo_3t_ckt---->resistor name]
How can i overcome it....

all reference libraries included in the list?
devicemap file set up correctly?
devicemap file enabled?

And also after importing,the MOSFET were assigned with minimum dimensions.
Is there any specific code in devicemap file to specify the MOSFET size(length,width,multiplier).......??????

"Device Properties to Match" set up correctly?

 

[jarillak]

Hi....

This is my devicemap file

-- Device Mapping file generated from SpiceIn GUI
devSelect := resistor rhrpo_3t_ckt
propMatch := R
termOrder := PLUS MINUS SUB
inhTerms := PLUS MINUS SUB
propMap := M W L
addProp := model rhrpo_3t_ckt

devSelect := pfet p12
termOrder := D G S B
propMap := w w m simM
addProp := model p12

devSelect := nfet n12
termOrder := D G S B
propMap := w w m simM
addProp := model n12

devSelect := capacitor mim1_ckt
termOrder := plus minus
propMap := l w m
addProp := model mim1_ckt



and also i set the technology library,analoglib for referencelibrary list

 

[erikl]

Shouldn't the fet propMaps be called

propMap := w [B]l[/B] m simM

Otherwise looks good. But I can't help you further. No more ideas, sorry!

 

[bsrin]

Hi erikl , Jarillak,

Jarillak,

Yes , you may be right. After translation from netlist to schematic. The devices (like nfet , pfet) shows the correct value on top , but when you see the values using properties of that device form you will obviously see the default values. This is because , every pdk devices will have their field callbacks which are executed when you change the corresponding fields.
You need to run all callbacks for all devices . You can get the "InvokeCallbacks.il" script from the cadence form. Run the script on the library which will updates the device properties like l,w,nf, etc...

Thanks.