Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

scheduling algorithm verification

Status
Not open for further replies.

ravi123

Junior Member level 1
Joined
Jan 3, 2005
Messages
15
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
88
the verification of scheduling algorithms

Can anyone suggest best way to verify scheduling algorithm RTL code.
how can i take care of timing mismatches between the reference model and RTL.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top