Scan shift and capture timing

[fail1]

How can we verify scan shift and capture timing in a design?
--Kumar

 

[VLSI@91]

hi,

can you be more clear with your question?

 

[jayh]

certainly by STA

 

[rca]

Scan shift signal does not "really" required used constraints. applying a max delay could be great just to avoid huge latency.

Scan capture, for me the clock distribution in scan mode, so with STA you could place with set_case_analysis the design in scan mode, and check the clock.
if you the backend flow is aready made by using the scan clock as the clock for the setup constraint, that should already covered.