Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

scan chain test fails

Status
Not open for further replies.

swordfisherman

Newbie level 3
Joined
Dec 16, 2013
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
23
I have scan mode both scan shift and scan capture STA pass, and Zero delay gatelevel simulation pass, but the simulation annotated with SDF fails, I use the same SDF check timing ,there is not timing violation, why the scan shift fail? I think STA clean means scan shift should be OK?
 

If your STA signoff is promising, maybe the error is caused by the asynchronous path if there are multiple scan clock.
The other reason maybe the relationship between active edge of clock and probe point for measurement.
It's better to check your simulated waveform for more details.
If possible, I hope that you can share your result. Thanks.
 

Are you using two different sessions for scan shift and scan capture in STA ?? You must be using a case analysis on the scan enable accordingly??
There may be multiple reason that its failing... Check the clock waveform timing first in STA session using report_clocks .. compare the duty cycle with what you have in the SPF file you're using in TMAX. These should preferably match.

Moreover investigate the timing violation and nail the flop giving violation. Do a report timing on that flop in PT.

There may be other reasons as well like due to improper annotation of the SDF, you're not even entering the test mode or the test mode is reset after a while.

So check the SDF annotation log too :)
 

Usually in GLS with SDF we check for the paths that we have set exceptions on..., because it is not possible to meet the requirements in STA. Now, when you do check_timing since you have applied constraints to those paths you will not see a violation. The tool waivers them.
Of course, there are many other possibilities but what you need to check is that for the paths failing GLS do you have any exceptions in STA constraint file ??
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top