Scan based testing is a method of testing internal logic in the chip by converting existing flip-flops in the design into scan chains, so that there are easily controllable and observable.
Boundary scan testing is a method of testing the connections external to the chip (mainly from the I/O pad through the package to the interconnects on the system board to another chip with boundary scan cells). This is done by adding boundary scan cells on the I/Os of the chip. Each boundary scan cell contains circuitry that can force logic on the outputs and capture logic on the inputs.
You can look at many previous posts on this forum for more info.