SAR ADC layouy

[the8thhabit]

I am currently designing and layout a 10-bit SAR ADC circuit.
In the figure above, the brown and purple lines represent the top plate nodes that switch during operation (i.e., Vinp and Vinn).

One issue I'm facing is that when I compare the presimulation (presim) and postsimulation (posim) waveforms, not only is the sampling not performed correctly, but also the voltage difference during CDAC switching is smaller than expected. In the presim results, the switching occurs with a 0.5 Vref difference (0.88 V and 0.44 V), but in the posim results, the switching is about 0.1 V less than expected. I believe this is due to the parasitic capacitance introduced in the layout, which is affecting the CDAC switching. Could you suggest layout techniques to reduce parasitic capacitance?

 

[nitishn5]

With Top Plate Sampling scheme that you have used, you are always going to have some amount of Gain Error.
You can reduce routing lengths, reduce the W, L of comparator input pair and all that to reduce the capacitance at the input of the Comparator.
But there will always be some amount left.

It is easier to just calibrate out the gain error.

 

[sidun.av]

View attachment 198914View attachment 198913
I am currently designing and layout a 10-bit SAR ADC circuit.
In the figure above, the brown and purple lines represent the top plate nodes that switch during operation (i.e., Vinp and Vinn).

One issue I'm facing is that when I compare the presimulation (presim) and postsimulation (posim) waveforms, not only is the sampling not performed correctly, but also the voltage difference during CDAC switching is smaller than expected. In the presim results, the switching occurs with a 0.5 Vref difference (0.88 V and 0.44 V), but in the posim results, the switching is about 0.1 V less than expected. I believe this is due to the parasitic capacitance introduced in the layout, which is affecting the CDAC switching. Could you suggest layout techniques to reduce parasitic capacitance?

1. It seems like your capacitor array doesn't use any matching. This will have a huge impact on performance and needs to be improved using the common centroid technique.
2. The main problem in your layout is drawing metal traces over capacitors - by doing this, you create a huge parasitic capacitor... Moreover, your routing is not symmetric, which will also impact the performance.

I can suggest the following:
1. Change placement to the common centroid;
2. Do not route metal traces on top of the capacitors. You can increase the spacing between unit caps for routing;
3. Try to keep your routing symmetric and weighted (less parasitic is allowed on LSB, more on MSB);
4. Minimize CDAC traces overlap to reduce parasitic loading.