SAR ADC data o/p clamp high by ideal dac ?

[wls]

Hello all. I have this problem with post simulation the data o/p ( D9..D0 ) is clamp high when ever I simulate it with ideal 10-bit dac ? Why is this happening , it works fine with funtional hspice ? When not connect and simulate with ideal dac the data from D9..D0 okay .

Below is the hspice for simulation .

Thx in advance.
****************************************************************
.OPTION POST=1
.OPTION numdgt=10
.temp 25

*.tran 11us 2000us
.tran 0.1n 30us

.lib 'cmos_x155.lib' typical
.lib 'mimos_analog_x135.lib' resistance_50
.lib '035_diode_model.lib' diodes
.options accurate=1

.include 'D:\Libero_IDE_7.3\mimos2007\test\comparator\compnew.dist'
.include 'D:\Libero_IDE_7.3\mimos2007\test\dac10\dac10.dist'
.include 'D:\Libero_IDE_7.3\mimos2007\test\sar10\sar10.dist'

**********START OF IDEALDAC circuit********************
.SUBCKT bitDAC VDD GND vref+ vref- vout B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
R1 VDD 100meg
R2 0 100meg
X9 B9 b9L BitLogic
X8 B8 b8L BitLogic
X7 B7 b7L BitLogic
X6 B6 b6L BitLogic
X5 B5 b5L BitLogic
X4 B4 b4L BitLogic
X3 B3 b3L BitLogic
X2 B2 b2L BitLogic
X1 B1 b1L BitLogic
X0 B0 b0L BitLogic

ETOTAL vout 0 VOL= '((V(vref+)-V(vref-))/1024)*((V(b9L)*512) + (V(b8L)*256) +(V(b7L)*128) + (V(b6L)*64) + (V(b5L)*32) +(V(b4L)*16) + (V(b3L)*8) + (V(b2L)*4) + (V(b1L)*2) + (V(b0L)) ) + (V(vref-)) '
.ends

.SUBCKT BitLogic BX BXL
Vone one 0 DC 1V
gs1 BXL one VCR PWL(1) BX 0 0v,1meg 3.3v,1
gs1c BXL 0 VCR PWL(1) BX 0 0v,1 3.3v,1meg
.ends


************************************************************************
* Library Name: ADC10
* Cell Name: ADC10
* View Name: schematic
************************************************************************

.SUBCKT ADC10 DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9>
+ clock eoc start VIN VRN VRP VDDA GNDA vdac
+ dac<0> dac<1> dac<2> dac<3> dac<4> dac<5> dac<6> dac<7> dac<8> dac<9> sample comp
*
*
XI2 vdac GNDA VRN VRP VDDA dac<0> dac<1> dac<2> dac<3> dac<4> dac<5> dac<6>
+ dac<7> dac<8> dac<9> DAC10
*
*
XI1 clock comp eoc dac<0> dac<1> dac<2> dac<3> dac<4> dac<5> dac<6> dac<7> dac<8> dac<9>
+ DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> sample start
+ GNDA VDDA SAR10
*
*
*XI0 VDDA SAMPLE OUT GNDA VDAC VIN COMPARATORNEW
X10 GNDA comp vdac VDDA VIN sample COMPARATOR
.ENDS
*********************************************************************************************************

XADC10 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 clock eoc start VIN VRN VRP VDDA GNDA vdac
+ dac<0> dac<1> dac<2> dac<3> dac<4> dac<5> dac<6> dac<7> dac<8> dac<9> sample comp ADC10

XbitDAC VDDA GNDA VRP VRN vout D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 bitDAC
XbitDAC2 VDDA GNDA VRP VRN vout2 dac<9> dac<8> dac<7> dac<6> dac<5> dac<4> dac<3> dac<2> dac<1> dac<0> bitDAC

VVDDA VDDA 0 dc 3.3v
VGNDA GNDA 0 dc 0v
VVDD VDD 0 dc 3.3v
VGND GND 0 dc 0v

Vclk clock 0 PULSE (0 3.3 0.01ns 0.01ns 0.01ns 0.5us 1us)
Vrefp VRP 0 DC 3.3V
Vrefm VRN 0 DC 0V
Vstart start 0 PWL(0ns,0V 100ns,0V 101ns,3.3)

VVIN VIN 0 PWL (0ns,0V 30us,3.3V)
*VVIN VIN cmo SIN 0 1 10k 0 0 0
*Vcmo cmo 0 DC 1.65

*VVIN VIN 0 sin (0 1.65 200k 1ns 0 0)
.fft V(vout) np=4096 window=hamming
.print V(VIN) V(clock) V(eoc) V(start) V(D0) V(D1) V(D2) V(D3) V(D4) V(D5) V(D6) V(D7) V(D8) V(D9)
.probe V(VIN) V(clock) V(eoc) V(start) V(D0) V(D1) V(D2) V(D3) V(D4) V(D5) V(D6) V(D7) V(D8) V(D9) V(vdac)
.PROBE V(dac<0>) V(dac<1>) V(dac<2>) V(dac<3>) V(dac<4>) V(dac<5>) V(dac<6>) V(dac<7>) V(dac<8>) V(dac<9>)
.PROBE V(sample) V(comp)
.PROBE V(vout)